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Change subject: payloads/edk2: Separate the build target and repository
......................................................................
Patch Set 27: Code-Review+2
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Change subject: payloads/edk2: Separate the build target and repository
......................................................................
Patch Set 27:
(1 comment)
Patchset:
PS27:
I like the structure of this approach, more neat and understandable, but still I will try to avoid to have another fork of edk2 repo again for UPL, as it will create extra discrepancies and maintenance burden. The main goal should be getting the fix merged into edk2 main repo and platform specific changes into forked edk2-platforms.
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Change subject: intel/i945: Use 'bool' for dual_channel and interleaved
......................................................................
Patch Set 3: Verified+1
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/68211
to look at the new patch set (#2).
Change subject: nb/intel/i945: Clean up includes
......................................................................
nb/intel/i945: Clean up includes
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
Change-Id: I0e5f102d75647c9c184cb7422af30c9196503882
---
M src/northbridge/intel/i945/errata.c
M src/northbridge/intel/i945/i945.h
M src/northbridge/intel/i945/romstage.c
3 files changed, 17 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/68211/2
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Change subject: intel/i945: Use 'bool' for dual_channel and interleaved
......................................................................
Patch Set 2:
(1 comment)
File src/northbridge/intel/i945/raminit.h:
https://review.coreboot.org/c/coreboot/+/67925/comment/02d71461_280c877c
PS2, Line 52: u8
> size_t ?
Ack
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Change subject: mb/google/brya/nivviks: Enable ISH driver and firmware name
......................................................................
Patch Set 1:
(2 comments)
File src/include/device/pci_ids.h:
https://review.coreboot.org/c/coreboot/+/68164/comment/a5aea246_f2b4d38f
PS1, Line 2185: ADL
> ADL_N? Based on the EDS the ADL-P ID is different.
Done
File src/mainboard/google/brya/Kconfig:
https://review.coreboot.org/c/coreboot/+/68164/comment/2454b773_96a922db
PS1, Line 76: select DRIVERS_INTEL_ISH
> nit: please keep them in alphabetical order
Done
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Hello build bot (Jenkins), Subrata Banik, Rizwan Qureshi, Reka Norman, Daniil Lunev, Divagar Mohandass,
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/brya/nivviks: Enable ISH driver and firmware name
......................................................................
mb/google/brya/nivviks: Enable ISH driver and firmware name
BRANCH=none
BUG=b:234776154
TEST=build and boot Nirwen UFS, copy ISH firmware to host
file system /lib/firmware/intel/adln_ish.bin
check "dmesg |grep ish", it should show:
ish-loader: ISH firmware intel/adlnrvp_ish.bin loaded
Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com>
Change-Id: I89782b0b7dde1fca0130472a38628e72dfd5c26c
---
M src/drivers/intel/ish/ish.c
M src/include/device/pci_ids.h
M src/mainboard/google/brya/Kconfig
M src/mainboard/google/brya/variants/nivviks/overridetree.cb
4 files changed, 24 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/68164/2
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Gerrit-MessageType: newpatchset
EricKY Cheng has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/68212 )
Change subject: spd/lp5: Add new memory configuration of H58G66BK7BX067 and H58G56BK7BX068
......................................................................
spd/lp5: Add new memory configuration of H58G66BK7BX067 and H58G56BK7BX068
Add Hynix H58G66BK7BX067 and H58G56BK7BX068 in the
memory_parts.json and re-generate the SPD.
BUG=b:243337816
BRANCH=None
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
Signed-off-by: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com>
Change-Id: I8d6aac3ecec36b126e7e41d6c9475695aa7a26b2
---
M spd/lp5/memory_parts.json
M spd/lp5/set-0/parts_spd_manifest.generated.txt
M spd/lp5/set-1/parts_spd_manifest.generated.txt
M spd/lp5/set-1/spd-7.hex
M spd/lp5/set-1/spd-8.hex
5 files changed, 45 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/68212/2
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Change subject: spd/lp5: Add new memory configuration of H58G66BK7BX067 and H58G56BK7BX068
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-159973):
https://review.coreboot.org/c/coreboot/+/68212/comment/441c0529_0004c54b
PS1, Line 9: Add Hynix H58G66BK7BX067 and H58G56BK7BX068 in the memory_parts.json and re-generate
Possible unwrapped commit description (prefer a maximum 72 chars per line)
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