coreboot-gerrit October 2022

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[M] Change in blobs[master]: mainboard/starlabs/starbook: Update the EC binaries for StarLabs
by Patrick Georgi (Code Review) 07 Oct '22

07 Oct '22

Attention is currently required from: Sean Rhodes. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/blobs/+/68016 ) Change subject: mainboard/starlabs/starbook: Update the EC binaries for StarLabs ...................................................................... Patch Set 4: Verified+1 Code-Review+2 (1 comment) Patchset: PS4: Thanks for the READMEs! -- To view, visit https://review.coreboot.org/c/blobs/+/68016 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: blobs Gerrit-Branch: master Gerrit-Change-Id: I2130852554388baf61b44091bfa827cb2b2f09e3 Gerrit-Change-Number: 68016 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Fri, 07 Oct 2022 11:22:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: [Only for test]i945/acpi/hostbridge.asl: include "i945.h"
by Elyes Haouas (Code Review) 07 Oct '22

07 Oct '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68219 ) Change subject: [Only for test]i945/acpi/hostbridge.asl: include "i945.h" ...................................................................... [Only for test]i945/acpi/hostbridge.asl: include "i945.h" Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Change-Id: I2abbacea44c456a80267e407ce47bd22787a72a9 --- M src/northbridge/intel/i945/acpi/hostbridge.asl M src/northbridge/intel/i945/i945.h 2 files changed, 23 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/68219/1 diff --git a/src/northbridge/intel/i945/acpi/hostbridge.asl b/src/northbridge/intel/i945/acpi/hostbridge.asl index 6eba415..199cc05 100644 --- a/src/northbridge/intel/i945/acpi/hostbridge.asl +++ b/src/northbridge/intel/i945/acpi/hostbridge.asl @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/ioapic.h> +#include <northbridge/intel/i945/i945.h> Name(_HID,EISAID("PNP0A08")) // PCIe Name(_CID,EISAID("PNP0A03")) // PCI @@ -14,30 +15,30 @@ OperationRegion(MCHP, PCI_Config, 0x00, 0x100) Field (MCHP, DWordAcc, NoLock, Preserve) { - Offset (0x40), /* EPBAR */ + Offset (EPBAR), EPEN, 1, /* Enable */ , 11, EPBR, 20, /* EPBAR */ - /* MCHBAR */ + Offset (MCHBAR), MHEN, 1, /* Enable */ , 13, MHBR, 18, /* MCHBAR */ - /* PCIe BAR */ + Offset (PCIEXBAR), PXEN, 1, /* Enable */ PXSZ, 2, /* BAR size */ , 23, PXBR, 6, /* PCIec BAR */ - /* DMIBAR */ + Offset (DMIBAR), DMEN, 1, /* Enable */ , 11, DMBR, 20, /* DMIBAR */ /* ... */ - Offset (0x90), /* PAM0 */ + Offset (PAM0), , 4, PM0H, 2, , 2, @@ -72,11 +73,11 @@ PM6H, 2, , 2, - Offset (0x9c), /* Top of Low Used Memory */ + Offset (TOLUD), , 3, TLUD, 5, - Offset (0xa0), /* Top of Used Memory */ + Offset (TOM), TOM, 16, } } diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index 4818a73..ac290c8 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -3,8 +3,10 @@ #ifndef NORTHBRIDGE_INTEL_I945_H #define NORTHBRIDGE_INTEL_I945_H +#ifndef __ACPI__ #include <northbridge/intel/common/fixed_bars.h> #include <southbridge/intel/i82801gx/i82801gx.h> +#endif #define DEFAULT_X60BAR 0xfed13000 @@ -321,6 +323,7 @@ #define DMIDRCCFG 0xeb4 /* 32bit */ +#ifndef __ACPI__ int i945_silicon_revision(void); void i945_early_initialization(void); void i945_late_initialization(int s3resume); @@ -345,4 +348,6 @@ /* Optional: mainboard callback to get SPD map */ void mainboard_get_spd_map(u8 spd_map[4]); +#endif /* __ACPI__ */ + #endif /* NORTHBRIDGE_INTEL_I945_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/68219 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2abbacea44c456a80267e407ce47bd22787a72a9 Gerrit-Change-Number: 68219 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: nb/intel/i945/i945.h: Drop useless guard
by Elyes Haouas (Code Review) 07 Oct '22

07 Oct '22

Attention is currently required from: Paul Menzel. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68215 ) Change subject: nb/intel/i945/i945.h: Drop useless guard ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/68215/comment/243f606b_0aebf682 PS1, Line 8: > Please elaborate. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/68215 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93bf96f8a86a2652a88f3a129ec197048dd914a4 Gerrit-Change-Number: 68215 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 07 Oct 2022 11:13:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: nb/intel/i945/i945.h: Drop useless guard
by Elyes Haouas (Code Review) 07 Oct '22

07 Oct '22

Attention is currently required from: Elyes Haouas. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68215 to look at the new patch set (#2). Change subject: nb/intel/i945/i945.h: Drop useless guard ...................................................................... nb/intel/i945/i945.h: Drop useless guard i945.h file is not used to generate asl files. Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Change-Id: I93bf96f8a86a2652a88f3a129ec197048dd914a4 --- M src/northbridge/intel/i945/i945.h 1 file changed, 12 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/68215/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68215 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93bf96f8a86a2652a88f3a129ec197048dd914a4 Gerrit-Change-Number: 68215 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: nb/intel/i945/raminit: Use 'bool' for do_reset
by Elyes Haouas (Code Review) 07 Oct '22

07 Oct '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68217 ) Change subject: nb/intel/i945/raminit: Use 'bool' for do_reset ...................................................................... nb/intel/i945/raminit: Use 'bool' for do_reset Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Change-Id: I692b86bba28853186185846f63dad1dcbfce1eea --- M src/northbridge/intel/i945/raminit.c 1 file changed, 15 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/68217/1 diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 58e5032..93b0a83 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -215,7 +215,7 @@ static void sdram_detect_errors(struct sys_info *sysinfo) { u8 reg8; - u8 do_reset = 0; + bool do_reset = false; reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2); @@ -224,7 +224,7 @@ printk(BIOS_DEBUG, "SLP S4# Assertion Width Violation.\n"); /* Write back clears bit 2 */ pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); - do_reset = 1; + do_reset = true; } @@ -232,7 +232,7 @@ printk(BIOS_DEBUG, "DRAM initialization was interrupted.\n"); reg8 &= ~(1 << 7); pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); - do_reset = 1; + do_reset = true; } /* Set SLP_S3# Assertion Stretch Enable */ @@ -257,12 +257,12 @@ if (((sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED) || (sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED)) && !(mchbar_read8(SLFRCS) & (1 << 0))) { - do_reset = 1; + do_reset = true; } if (((sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED) || (sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)) && !(mchbar_read8(SLFRCS) & (1 << 1))) { - do_reset = 1; + do_reset = true; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/68217 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I692b86bba28853186185846f63dad1dcbfce1eea Gerrit-Change-Number: 68217 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: nb/intel/i945/raminit: Use 'bool' for clkcfg_bit7
by Elyes Haouas (Code Review) 07 Oct '22

07 Oct '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68216 ) Change subject: nb/intel/i945/raminit: Use 'bool' for clkcfg_bit7 ...................................................................... nb/intel/i945/raminit: Use 'bool' for clkcfg_bit7 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Change-Id: Ia87fbbeb9ecb57ee2f4879404cbae5403de9bfc7 --- M src/northbridge/intel/i945/raminit.c M src/northbridge/intel/i945/raminit.h 2 files changed, 16 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/68216/1 diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 7b0d6d2..58e5032 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -1603,7 +1603,8 @@ static void sdram_program_graphics_frequency(struct sys_info *sysinfo) { u8 reg8; - u8 freq, second_vco, voltage; + u8 freq, voltage; + bool second_vco = false; #define CRCLK_166MHz 0x00 #define CRCLK_200MHz 0x01 @@ -1679,10 +1680,8 @@ else sysinfo->mvco4x = 0; - second_vco = 0; - if (voltage == VOLTAGE_1_50) { - second_vco = 1; + second_vco = true; } else if ((i945_silicon_revision() > 0) && (freq == CRCLK_250MHz)) { u16 mem = sysinfo->memory_frequency; u16 fsb = sysinfo->fsb_frequency; @@ -1690,17 +1689,14 @@ if ((fsb == 667 && mem == 533) || (fsb == 533 && mem == 533) || (fsb == 533 && mem == 400)) { - second_vco = 1; + second_vco = true; } if (fsb == 667 && mem == 533) sysinfo->mvco4x = 1; } - if (second_vco) - sysinfo->clkcfg_bit7 = 1; - else - sysinfo->clkcfg_bit7 = 0; + sysinfo->clkcfg_bit7 = second_vco; /* Graphics Core Render Clock */ pci_update_config16(IGD_DEV, GCFC, ~((7 << 0) | (1 << 13)), freq); diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h index efaedf4..22c4faf 100644 --- a/src/northbridge/intel/i945/raminit.h +++ b/src/northbridge/intel/i945/raminit.h @@ -30,7 +30,7 @@ bool interleaved; u8 mvco4x; /* 0 (8x) or 1 (4x) */ - u8 clkcfg_bit7; + bool clkcfg_bit7; u8 boot_path; #define BOOT_PATH_NORMAL 0 #define BOOT_PATH_RESET 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/68216 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia87fbbeb9ecb57ee2f4879404cbae5403de9bfc7 Gerrit-Change-Number: 68216 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: cpu/intel/common/fsb.c: Sorte includes and add <stdint.h>
by Paul Menzel (Code Review) 07 Oct '22

07 Oct '22

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68041 ) Change subject: cpu/intel/common/fsb.c: Sorte includes and add <stdint.h> ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/68041/comment/553ac1c5_7db32730 PS2, Line 7: cpu/intel/common/fsb.c: Sorte includes and add <stdint.h> Sort -- To view, visit https://review.coreboot.org/c/coreboot/+/68041 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b85836ac21da5b885a97f05e3973fb23a052fd5 Gerrit-Change-Number: 68041 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 07 Oct 2022 10:00:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: 3rdparty/amd_blobs:Advance submodule pointer
by Paul Menzel (Code Review) 07 Oct '22

07 Oct '22

Attention is currently required from: Jason Glenesk, Karthik Ramasubramanian. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68115 ) Change subject: 3rdparty/amd_blobs:Advance submodule pointer ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/68115/comment/c81c6aac_beb65f9e PS2, Line 7: 3rdparty/amd_blobs:Advance submodule pointer Please add a space after the colon. -- To view, visit https://review.coreboot.org/c/coreboot/+/68115 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia28bba399ed527863f18ecd790c7096254873298 Gerrit-Change-Number: 68115 Gerrit-PatchSet: 2 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 07 Oct 2022 10:00:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: nb/intel/i945/i945.h: Drop useless guard
by Paul Menzel (Code Review) 07 Oct '22

07 Oct '22

Attention is currently required from: Elyes Haouas. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68215 ) Change subject: nb/intel/i945/i945.h: Drop useless guard ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/68215/comment/20ad12cc_2fffed4f PS1, Line 8: Please elaborate. -- To view, visit https://review.coreboot.org/c/coreboot/+/68215 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93bf96f8a86a2652a88f3a129ec197048dd914a4 Gerrit-Change-Number: 68215 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 07 Oct 2022 10:00:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: nb/intel/i945/i945.h: Drop useless guard
by Elyes Haouas (Code Review) 07 Oct '22

07 Oct '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68215 ) Change subject: nb/intel/i945/i945.h: Drop useless guard ...................................................................... nb/intel/i945/i945.h: Drop useless guard Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Change-Id: I93bf96f8a86a2652a88f3a129ec197048dd914a4 --- M src/northbridge/intel/i945/i945.h 1 file changed, 10 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/68215/1 diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index 3470a77..4818a73 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -8,9 +8,6 @@ #define DEFAULT_X60BAR 0xfed13000 -/* Everything below this line is ignored in the DSDT */ -#ifndef __ACPI__ - /* Display defines for the interrupt 15h handler */ #define INT15_5F35_CL_DISPLAY_DEFAULT 0 #define INT15_5F35_CL_DISPLAY_CRT (1 << 0) @@ -348,6 +345,4 @@ /* Optional: mainboard callback to get SPD map */ void mainboard_get_spd_map(u8 spd_map[4]); -#endif /* __ACPI__ */ - #endif /* NORTHBRIDGE_INTEL_I945_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/68215 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93bf96f8a86a2652a88f3a129ec197048dd914a4 Gerrit-Change-Number: 68215 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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coreboot-gerrit October 2022