coreboot-gerrit October 2022

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: Update amd_blobs submodule to upstream master
by Marshall Dawson (Code Review) 07 Oct '22

07 Oct '22

Attention is currently required from: Martin L Roth, Martin Roth. Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68190 ) Change subject: Update amd_blobs submodule to upstream master ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id55c468721ac42ecd71e8e3d1fa1cb4887a98c99 Gerrit-Change-Number: 68190 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Fri, 07 Oct 2022 17:11:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/rex: Add initial fw config
by Kapil Porwal (Code Review) 07 Oct '22

07 Oct '22

Attention is currently required from: Tarun Tuli, Subrata Banik. Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68220 to look at the new patch set (#3). Change subject: mb/google/rex: Add initial fw config ...................................................................... mb/google/rex: Add initial fw config Add initial fw config as per config.star. BUG=none TEST=emerge-rex coreboot. Make sure that ACPI tables are equivalent before and affter this change. Signed-off-by: Kapil Porwal <kapilporwal(a)google.com> Change-Id: I66f8b3e4ab414c03b8d63fdd31e0f3f424619340 --- M src/mainboard/google/rex/variants/rex0/overridetree.cb 1 file changed, 94 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/68220/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/68220 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66f8b3e4ab414c03b8d63fdd31e0f3f424619340 Gerrit-Change-Number: 68220 Gerrit-PatchSet: 3 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: Update amd_blobs submodule to upstream master
by Fred Reitberger (Code Review) 07 Oct '22

07 Oct '22

Attention is currently required from: Martin L Roth, Martin Roth. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68190 ) Change subject: Update amd_blobs submodule to upstream master ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/68190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id55c468721ac42ecd71e8e3d1fa1cb4887a98c99 Gerrit-Change-Number: 68190 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Fri, 07 Oct 2022 16:58:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: [UNTESTED] mb/siemens/mc_apl2: Try to make early PCIe work
by Angel Pons (Code Review) 07 Oct '22

07 Oct '22

Attention is currently required from: Werner Zeh, Jan Samek. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68223 ) Change subject: [UNTESTED] mb/siemens/mc_apl2: Try to make early PCIe work ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: If it works, feel free to make it pretty. Doing this on all APL boards seems unnecessary, and could cause problems if PERST# is used. -- To view, visit https://review.coreboot.org/c/coreboot/+/68223 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If782bfdd5f499dd47c085a0a16b4b15832bc040e Gerrit-Change-Number: 68223 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Jan Samek <jan.samek(a)siemens.com> Gerrit-Comment-Date: Fri, 07 Oct 2022 16:32:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/prodrive/atlas: Print HSID
by Maximilian Brune (Code Review) 07 Oct '22

07 Oct '22

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68224 ) Change subject: mb/prodrive/atlas: Print HSID ...................................................................... mb/prodrive/atlas: Print HSID Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: Ibb7aac1204bc297d16797cac5b32b119d0a9204b --- M src/mainboard/prodrive/atlas/gpio.c M src/mainboard/prodrive/atlas/mainboard.c 2 files changed, 27 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/68224/1 diff --git a/src/mainboard/prodrive/atlas/gpio.c b/src/mainboard/prodrive/atlas/gpio.c index 5d67aa7..66e5e72 100644 --- a/src/mainboard/prodrive/atlas/gpio.c +++ b/src/mainboard/prodrive/atlas/gpio.c @@ -7,6 +7,7 @@ /* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_GPI(GPP_A8, NONE, RSMRST), /* HSID_0 */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* USB_2_3_OC_N */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), /* USB_4_5_OC_N */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* USB_6_7_OC_N */ @@ -59,6 +60,7 @@ PAD_CFG_GPO(GPP_F9, 1, DEEP), /* EC_SLP_S0_CS_N */ PAD_CFG_GPI(GPP_F12, NONE, DEEP), PAD_CFG_GPI(GPP_F13, NONE, DEEP), + PAD_CFG_GPI(GPP_F19, NONE, RSMRST), /* HSID_1 */ PAD_NC(GPP_F20, NONE), PAD_NC(GPP_F21, NONE), PAD_CFG_GPO(GPP_F22, 1, DEEP), /* PERST_PHY0_N */ @@ -66,6 +68,8 @@ /* ------- GPIO Group GPP_H ------- */ PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), /* DDPB_CTRLDATA */ + PAD_CFG_GPI(GPP_H19, NONE, RSMRST), /* HSID_3 */ + PAD_CFG_GPI(GPP_H23, NONE, RSMRST), /* HSID_2 */ /* ------- GPIO Group GPP_R ------- */ PAD_CFG_NF(GPP_R5, NONE, DEEP, NF1), /* HDA_SDI1 */ diff --git a/src/mainboard/prodrive/atlas/mainboard.c b/src/mainboard/prodrive/atlas/mainboard.c index 036208a..89571c7 100644 --- a/src/mainboard/prodrive/atlas/mainboard.c +++ b/src/mainboard/prodrive/atlas/mainboard.c @@ -1,13 +1,26 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/device.h> +#include <console/console.h> #include <stdint.h> +#include <gpio.h> +#include <arch/io.h> #include "gpio.h" +static void print_hsid(void) +{ + uint8_t hsid = gpio_get(GPP_A8); + hsid |= gpio_get(GPP_F19) < 1; + hsid |= gpio_get(GPP_H23) < 2; + hsid |= gpio_get(GPP_H19) < 3; + printk(BIOS_INFO, "HSID: 0x%1x\n", hsid); +} + static void mainboard_init(void *chip_info) { configure_gpio_pads(); + print_hsid(); } struct chip_operations mainboard_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/68224 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb7aac1204bc297d16797cac5b32b119d0a9204b Gerrit-Change-Number: 68224 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: [UNTESTED] mb/siemens/mc_apl2: Try to make early PCIe work
by Angel Pons (Code Review) 07 Oct '22

07 Oct '22

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68223 ) Change subject: [UNTESTED] mb/siemens/mc_apl2: Try to make early PCIe work ...................................................................... [UNTESTED] mb/siemens/mc_apl2: Try to make early PCIe work FSP-M seems to do something to make PCIe ports work. However, we need to have PCIe ports working in bootblock for the NC FPGA. Add a bit of magic register poking that (hopefully) allows the PCIe ports to work earlier. UNTESTED. Change-Id: If782bfdd5f499dd47c085a0a16b4b15832bc040e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/siemens/mc_apl1/bootblock.c 1 file changed, 44 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/68223/1 diff --git a/src/mainboard/siemens/mc_apl1/bootblock.c b/src/mainboard/siemens/mc_apl1/bootblock.c index a858f1b..aaf8eb9 100644 --- a/src/mainboard/siemens/mc_apl1/bootblock.c +++ b/src/mainboard/siemens/mc_apl1/bootblock.c @@ -2,7 +2,32 @@ #include <baseboard/variants.h> #include <bootblock_common.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> #include <intelblocks/gpio.h> +#include <types.h> + +static void try_to_make_pcie_work(void) +{ + const pci_devfn_t pcie_rps[] = { + PCI_DEV(0, 0x13, 0), PCI_DEV(0, 0x13, 1), PCI_DEV(0, 0x13, 2), + PCI_DEV(0, 0x13, 3), PCI_DEV(0, 0x14, 0), PCI_DEV(0, 0x14, 1), + }; + + for (unsigned int i = 0; i < ARRAY_SIZE(pcie_rps); i++) { + const pci_devfn_t dev = pcie_rps[i]; + + if (pci_read_config16(dev, PCI_VENDOR_ID) == 0xffff) + continue; + + /* + * Needs to be done "immediately after PERST# de-assertion" + * as per IAFW spec volume 2 (doc 559810) + */ + pci_and_config32(dev, 0x338, ~(1 << 26)); /* BLKDQDA */ + pci_and_config32(dev, 0xf4, ~(1 << 2)); /* BLKPLLEN */ + } +} void bootblock_mainboard_early_init(void) { @@ -11,4 +36,7 @@ pads = variant_early_gpio_table(&num); gpio_configure_pads(pads, num); + + if (CONFIG(BOARD_SIEMENS_MC_APL2)) + try_to_make_pcie_work(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/68223 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If782bfdd5f499dd47c085a0a16b4b15832bc040e Gerrit-Change-Number: 68223 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/prodrive/atlas: Disable C-States & cTDP
by Lean Sheng Tan (Code Review) 07 Oct '22

07 Oct '22

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68222 ) Change subject: mb/prodrive/atlas: Disable C-States & cTDP ...................................................................... mb/prodrive/atlas: Disable C-States & cTDP As Atlas is required for industrial use cases: - Disable Configurable TDP - Disable all C-states other than C0/C1 for CPU and package Signed-off-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Change-Id: Iaf1c15ac258c78025420966bf592795b66101d17 --- M src/mainboard/prodrive/atlas/mainboard.c 1 file changed, 27 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/68222/1 diff --git a/src/mainboard/prodrive/atlas/mainboard.c b/src/mainboard/prodrive/atlas/mainboard.c index 036208a..65b266f 100644 --- a/src/mainboard/prodrive/atlas/mainboard.c +++ b/src/mainboard/prodrive/atlas/mainboard.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/device.h> +#include <soc/ramstage.h> #include <stdint.h> #include "gpio.h" @@ -10,6 +11,18 @@ configure_gpio_pads(); } +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + /* Disable CPU power states (C-states) */ + params->Cx = 0; + + /* Set maximum package C-state to PkgC0C1 */ + params->PkgCStateLimit = 0; + + /* Disable Configurable TDP */ + params->ApplyConfigTdp = 0; +} + struct chip_operations mainboard_ops = { .init = mainboard_init, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/68222 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf1c15ac258c78025420966bf592795b66101d17 Gerrit-Change-Number: 68222 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: newchange

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[XL] Change in coreboot[master]: payloads/cbui: Add new payload CBUI
by Iman Bingi (Code Review) 07 Oct '22

07 Oct '22

Attention is currently required from: Iman Bingi, Martin L Roth, Julius Werner, Patrick Rudolph. Iman Bingi has uploaded a new patch set (#74) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/23586 ) Change subject: payloads/cbui: Add new payload CBUI ...................................................................... payloads/cbui: Add new payload CBUI Depends on libpayload and nuklear. Features: * Graphical menus with scrolling. * Text rendering engine (atm only bitmap font) * Support for keyboard and mouse * Support for USB and PS/2 devices * Ported coreinfo and nvramcui * Allows to modify NVRAM and RTC * Works as ELF payload * Works as Seabios secondary payload * Basic support for multiple languages * Hacky support for BIOS calls (depends on NASM) * Runs in qemu and on real hardware * Use linker script to allocate low memory Shortcomings: * Doesn't work in VGA text mode * Untested on UEFI * int32 relocates itself to low memory Licenses: * GPLv2 (CBUI + libpayload) * BSD (libpayload) * MIT (nuklear) TODO: * Test on as much platforms as possible * Link int32 into low memory This is Patrick Rudolph's original patch, updated by Ben Adu-Boahen to: * Add Read/Write module * This module allows read/write to any hardware component that is readable/writeable Note: This is work in progress Change-Id: Ib9a1a07c1065880aa675380625021750d5cab7d1 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Signed-off-by: Ben Adu-Boahen <imanbingy(a)gmail.com> --- M payloads/Kconfig M payloads/Makefile.inc A payloads/cbui/.gitignore A payloads/cbui/Kconfig A payloads/cbui/Makefile A payloads/cbui/NuklearUI/NuklearCombo.c A payloads/cbui/NuklearUI/NuklearCombo.h A payloads/cbui/NuklearUI/NuklearCommon.h A payloads/cbui/NuklearUI/NuklearDataGrid.c A payloads/cbui/NuklearUI/NuklearDataGrid.h A payloads/cbui/NuklearUI/NuklearDatePicker.c A payloads/cbui/NuklearUI/NuklearDatePicker.h A payloads/cbui/NuklearUI/NuklearFieldFile.c A payloads/cbui/NuklearUI/NuklearFieldFile.h A payloads/cbui/NuklearUI/NuklearFieldHex.c A payloads/cbui/NuklearUI/NuklearFieldHex.h A payloads/cbui/NuklearUI/NuklearFileChooser.c A payloads/cbui/NuklearUI/NuklearFileChooser.h A payloads/cbui/NuklearUI/NuklearGroup.c A payloads/cbui/NuklearUI/NuklearGroup.h A payloads/cbui/NuklearUI/NuklearHex.c A payloads/cbui/NuklearUI/NuklearHex.h A payloads/cbui/NuklearUI/NuklearIntegerRange.c A payloads/cbui/NuklearUI/NuklearIntegerRange.h A payloads/cbui/NuklearUI/NuklearLabel.c A payloads/cbui/NuklearUI/NuklearLabel.h A payloads/cbui/NuklearUI/NuklearObject.c A payloads/cbui/NuklearUI/NuklearObject.h A payloads/cbui/NuklearUI/NuklearPciHeader.c A payloads/cbui/NuklearUI/NuklearPciHeader.h A payloads/cbui/NuklearUI/NuklearRW.c A payloads/cbui/NuklearUI/NuklearRW.h A payloads/cbui/NuklearUI/NuklearRoot.c A payloads/cbui/NuklearUI/NuklearRwAcpi.c A payloads/cbui/NuklearUI/NuklearRwAcpi.h A payloads/cbui/NuklearUI/NuklearRwAtaAtapi.c A payloads/cbui/NuklearUI/NuklearRwAtaAtapi.h A payloads/cbui/NuklearUI/NuklearRwClock.c A payloads/cbui/NuklearUI/NuklearRwClock.h A payloads/cbui/NuklearUI/NuklearRwCpuMsr.c A payloads/cbui/NuklearUI/NuklearRwCpuMsr.h A payloads/cbui/NuklearUI/NuklearRwDimmSpd.c A payloads/cbui/NuklearUI/NuklearRwDimmSpd.h A payloads/cbui/NuklearUI/NuklearRwE820.c A payloads/cbui/NuklearUI/NuklearRwE820.h A payloads/cbui/NuklearUI/NuklearRwEc.c A payloads/cbui/NuklearUI/NuklearRwEc.h A payloads/cbui/NuklearUI/NuklearRwIo.c A payloads/cbui/NuklearUI/NuklearRwIo.h A payloads/cbui/NuklearUI/NuklearRwIoIndexData.c A payloads/cbui/NuklearUI/NuklearRwIoIndexData.h A payloads/cbui/NuklearUI/NuklearRwMemory.c A payloads/cbui/NuklearUI/NuklearRwMemory.h A payloads/cbui/NuklearUI/NuklearRwMemoryIndexData.c A payloads/cbui/NuklearUI/NuklearRwMemoryIndexData.h A payloads/cbui/NuklearUI/NuklearRwNvram.c A payloads/cbui/NuklearUI/NuklearRwNvram.h A payloads/cbui/NuklearUI/NuklearRwPci.c A payloads/cbui/NuklearUI/NuklearRwPci.h A payloads/cbui/NuklearUI/NuklearRwPciIndexData.c A payloads/cbui/NuklearUI/NuklearRwPciIndexData.h A payloads/cbui/NuklearUI/NuklearRwPciOptionRom.c A payloads/cbui/NuklearUI/NuklearRwPciOptionRom.h A payloads/cbui/NuklearUI/NuklearRwSmbios.c A payloads/cbui/NuklearUI/NuklearRwSmbios.h A payloads/cbui/NuklearUI/NuklearRwSmbus.c A payloads/cbui/NuklearUI/NuklearRwSmbus.h A payloads/cbui/NuklearUI/NuklearRwSmram.c A payloads/cbui/NuklearUI/NuklearRwSmram.h A payloads/cbui/NuklearUI/NuklearRwSuperIo.c A payloads/cbui/NuklearUI/NuklearRwSuperIo.h A payloads/cbui/NuklearUI/NuklearRwUsb.c A payloads/cbui/NuklearUI/NuklearRwUsb.h A payloads/cbui/NuklearUI/NuklearStyle.c A payloads/cbui/NuklearUI/NuklearStyle.h A payloads/cbui/NuklearUI/NuklearTabView.c A payloads/cbui/NuklearUI/NuklearTextView.c A payloads/cbui/NuklearUI/NuklearTextView.h A payloads/cbui/NuklearUI/NuklearTextfield.c A payloads/cbui/NuklearUI/NuklearTextfield.h A payloads/cbui/NuklearUI/NuklearTimePicker.c A payloads/cbui/NuklearUI/NuklearTimePicker.h A payloads/cbui/NuklearUI/NuklearUI.h A payloads/cbui/NuklearUI/NuklearVector.c A payloads/cbui/NuklearUI/NuklearVector.h A payloads/cbui/arch/x86/cpuid.c A payloads/cbui/arch/x86/cpuid.h A payloads/cbui/arch/x86/int32.h A payloads/cbui/arch/x86/int32.ld A payloads/cbui/arch/x86/int32.nasm A payloads/cbui/arch/x86/memcpy.c A payloads/cbui/arch/x86/memcpy.h A payloads/cbui/arch/x86/vga.c A payloads/cbui/arch/x86/vga.h A payloads/cbui/cbui.c A payloads/cbui/cbui.h A payloads/cbui/fsys/usbstorage.c A payloads/cbui/fsys/usbstorage.h A payloads/cbui/gfx/coreboot.c A payloads/cbui/gfx/coreboot.h A payloads/cbui/gfx/gfx.c A payloads/cbui/gfx/gfx.h A payloads/cbui/gfx/splash.c A payloads/cbui/gfx/splash.h A payloads/cbui/gfx/vbe.c A payloads/cbui/gfx/vbe.h A payloads/cbui/lang/de.c A payloads/cbui/lang/en.c A payloads/cbui/lang/lang.c A payloads/cbui/lang/lang.h A payloads/cbui/logo/cbui.png A payloads/cbui/lp.config A payloads/cbui/modules/bootlog_module.c A payloads/cbui/modules/cbfs_module.c A payloads/cbui/modules/cmos_module.c A payloads/cbui/modules/coreboot_module.c A payloads/cbui/modules/cpuinfo_module.c A payloads/cbui/modules/license_module.c A payloads/cbui/modules/modules.c A payloads/cbui/modules/modules.h A payloads/cbui/modules/nvram_module.c A payloads/cbui/modules/pci_module.c A payloads/cbui/modules/reboot_module.c A payloads/cbui/modules/rtc_module.c A payloads/cbui/modules/rw_module.c A payloads/cbui/modules/timestamps_module.c A payloads/cbui/modules/usb_module.c A payloads/libpayload/configs/defconfig-cbui 128 files changed, 15,600 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/23586/74 -- To view, visit https://review.coreboot.org/c/coreboot/+/23586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9a1a07c1065880aa675380625021750d5cab7d1 Gerrit-Change-Number: 23586 Gerrit-PatchSet: 74 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Iman Bingi <imanbingy(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Iman Bingi <imanbingy(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: spd/lp5: Add new memory configuration of H58G66BK7BX067 and H58G56BK7...
by Tim Van Patten (Code Review) 07 Oct '22

07 Oct '22

Attention is currently required from: Raul Rangel, EricKY Cheng, Martin Roth, Moises Garcia, Eric Peers, Karthikeyan Ramasubramanian. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68212 ) Change subject: spd/lp5: Add new memory configuration of H58G66BK7BX067 and H58G56BK7BX068 ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/68212/comment/dc6098b5_cbde89aa PS2, Line 14: TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Which boards does this affect? Since we've had issues with other LP5x CLs - have you verified the board can boot with these changes? -- To view, visit https://review.coreboot.org/c/coreboot/+/68212 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d6aac3ecec36b126e7e41d6c9475695aa7a26b2 Gerrit-Change-Number: 68212 Gerrit-PatchSet: 2 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Moises Garcia <moisesgarcia(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Moises Garcia <moisesgarcia(a)google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Comment-Date: Fri, 07 Oct 2022 16:04:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: spd/lp5: Add new memory configuration of H9JCNNNFA5MLYR-N6E
by Chao Gui (Code Review) 07 Oct '22

07 Oct '22

Attention is currently required from: Frank Wu, Kangheui Won, Isaac Lee, Tim Wawrzynczak, Martin Roth, Karthik Ramasubramanian. Chao Gui has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68154 ) Change subject: spd/lp5: Add new memory configuration of H9JCNNNFA5MLYR-N6E ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/68154 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9926a5859cf060e0bfa903f47d8a98c8d6115579 Gerrit-Change-Number: 68154 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chao Gui <chaogui(a)google.com> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Isaac Lee <isaaclee(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 07 Oct 2022 15:39:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit October 2022