coreboot-gerrit October 2022

coreboot-gerrit@coreboot.org

1 participants
5881 discussions

[M] Change in coreboot[master]: util/amdfwtool/amdfwread: Handle recovery A/B layout
by Raul Rangel (Code Review) 20 Oct '22

20 Oct '22

Attention is currently required from: Robert Zieba, Bao Zheng, Jon Murphy, Rob Barnes, Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66554 ) Change subject: util/amdfwtool/amdfwread: Handle recovery A/B layout ...................................................................... Patch Set 14: (1 comment) File util/amdfwtool/amdfwread.c: https://review.coreboot.org/c/coreboot/+/66554/comment/2936d954_fe812aea PS14, Line 157: break > This is the break for the case statement so that we dont fallthrough to the next case. […] lol thanks for pointing that out :) -- To view, visit https://review.coreboot.org/c/coreboot/+/66554 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6576eaebc611ab338885aed2ee087bf85da3ca15 Gerrit-Change-Number: 66554 Gerrit-PatchSet: 14 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 20 Oct 2022 18:31:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

1 0

[XL] Change in coreboot[master]: payloads/cbui: Add new payload CBUI
by Iman Bingi (Code Review) 20 Oct '22

20 Oct '22

Attention is currently required from: Iman Bingi, Martin L Roth, Julius Werner, Patrick Rudolph. Iman Bingi has uploaded a new patch set (#164) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/23586 ) Change subject: payloads/cbui: Add new payload CBUI ...................................................................... payloads/cbui: Add new payload CBUI Depends on libpayload and nuklear. Features: * Graphical menus with scrolling. * Text rendering engine (atm only bitmap font) * Support for keyboard and mouse * Support for USB and PS/2 devices * Ported coreinfo and nvramcui * Allows to modify NVRAM and RTC * Works as ELF payload * Works as Seabios secondary payload * Basic support for multiple languages * Hacky support for BIOS calls (depends on NASM) * Runs in qemu and on real hardware * Use linker script to allocate low memory Shortcomings: * Doesn't work in VGA text mode * Untested on UEFI * int32 relocates itself to low memory Licenses: * GPLv2 (CBUI + libpayload) * BSD (libpayload) * MIT (nuklear) TODO: * Test on as much platforms as possible * Link int32 into low memory This is Patrick Rudolph's original patch, updated by Ben Adu-Boahen to: * Add Read/Write module * This module allows read/write to any hardware component that is readable/writeable Note: This is work in progress Change-Id: Ib9a1a07c1065880aa675380625021750d5cab7d1 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Signed-off-by: Ben Adu-Boahen <imanbingy(a)gmail.com> --- M payloads/Kconfig M payloads/Makefile.inc A payloads/cbui/.gitignore A payloads/cbui/Kconfig A payloads/cbui/Makefile A payloads/cbui/NuklearUI/NuklearCheckbox.c A payloads/cbui/NuklearUI/NuklearCheckbox.h A payloads/cbui/NuklearUI/NuklearCombo.c A payloads/cbui/NuklearUI/NuklearCombo.h A payloads/cbui/NuklearUI/NuklearCommon.h A payloads/cbui/NuklearUI/NuklearDataGrid.c A payloads/cbui/NuklearUI/NuklearDataGrid.h A payloads/cbui/NuklearUI/NuklearDatePicker.c A payloads/cbui/NuklearUI/NuklearDatePicker.h A payloads/cbui/NuklearUI/NuklearFieldFile.c A payloads/cbui/NuklearUI/NuklearFieldFile.h A payloads/cbui/NuklearUI/NuklearFieldHex.c A payloads/cbui/NuklearUI/NuklearFieldHex.h A payloads/cbui/NuklearUI/NuklearFileChooser.c A payloads/cbui/NuklearUI/NuklearFileChooser.h A payloads/cbui/NuklearUI/NuklearGroup.c A payloads/cbui/NuklearUI/NuklearGroup.h A payloads/cbui/NuklearUI/NuklearHex.c A payloads/cbui/NuklearUI/NuklearHex.h A payloads/cbui/NuklearUI/NuklearIntegerRange.c A payloads/cbui/NuklearUI/NuklearIntegerRange.h A payloads/cbui/NuklearUI/NuklearLabel.c A payloads/cbui/NuklearUI/NuklearLabel.h A payloads/cbui/NuklearUI/NuklearObject.c A payloads/cbui/NuklearUI/NuklearObject.h A payloads/cbui/NuklearUI/NuklearRW.c A payloads/cbui/NuklearUI/NuklearRW.h A payloads/cbui/NuklearUI/NuklearRoot.c A payloads/cbui/NuklearUI/NuklearRwAcpi.c A payloads/cbui/NuklearUI/NuklearRwAcpi.h A payloads/cbui/NuklearUI/NuklearRwAtaAtapi.c A payloads/cbui/NuklearUI/NuklearRwAtaAtapi.h A payloads/cbui/NuklearUI/NuklearRwDimmSpd.c A payloads/cbui/NuklearUI/NuklearRwDimmSpd.h A payloads/cbui/NuklearUI/NuklearRwEc.c A payloads/cbui/NuklearUI/NuklearRwEc.h A payloads/cbui/NuklearUI/NuklearRwIo.c A payloads/cbui/NuklearUI/NuklearRwIo.h A payloads/cbui/NuklearUI/NuklearRwIoIndexData.c A payloads/cbui/NuklearUI/NuklearRwIoIndexData.h A payloads/cbui/NuklearUI/NuklearRwMemory.c A payloads/cbui/NuklearUI/NuklearRwMemory.h A payloads/cbui/NuklearUI/NuklearRwMemoryIndexData.c A payloads/cbui/NuklearUI/NuklearRwMemoryIndexData.h A payloads/cbui/NuklearUI/NuklearRwNvram.c A payloads/cbui/NuklearUI/NuklearRwNvram.h A payloads/cbui/NuklearUI/NuklearRwPci.c A payloads/cbui/NuklearUI/NuklearRwPci.h A payloads/cbui/NuklearUI/NuklearRwPciIndexData.c A payloads/cbui/NuklearUI/NuklearRwPciIndexData.h A payloads/cbui/NuklearUI/NuklearRwSuperIo.c A payloads/cbui/NuklearUI/NuklearRwSuperIo.h A payloads/cbui/NuklearUI/NuklearStyle.c A payloads/cbui/NuklearUI/NuklearStyle.h A payloads/cbui/NuklearUI/NuklearTabView.c A payloads/cbui/NuklearUI/NuklearTextView.c A payloads/cbui/NuklearUI/NuklearTextView.h A payloads/cbui/NuklearUI/NuklearTextfield.c A payloads/cbui/NuklearUI/NuklearTextfield.h A payloads/cbui/NuklearUI/NuklearTimePicker.c A payloads/cbui/NuklearUI/NuklearTimePicker.h A payloads/cbui/NuklearUI/NuklearUI.h A payloads/cbui/NuklearUI/NuklearVector.c A payloads/cbui/NuklearUI/NuklearVector.h A payloads/cbui/arch/x86/cpuid.c A payloads/cbui/arch/x86/cpuid.h A payloads/cbui/arch/x86/int32.h A payloads/cbui/arch/x86/int32.ld A payloads/cbui/arch/x86/int32.nasm A payloads/cbui/arch/x86/memcpy.c A payloads/cbui/arch/x86/memcpy.h A payloads/cbui/arch/x86/vga.c A payloads/cbui/arch/x86/vga.h A payloads/cbui/cbui.c A payloads/cbui/cbui.h A payloads/cbui/fsys/usbstorage.c A payloads/cbui/fsys/usbstorage.h A payloads/cbui/gfx/coreboot.c A payloads/cbui/gfx/coreboot.h A payloads/cbui/gfx/gfx.c A payloads/cbui/gfx/gfx.h A payloads/cbui/gfx/splash.c A payloads/cbui/gfx/splash.h A payloads/cbui/gfx/vbe.c A payloads/cbui/gfx/vbe.h A payloads/cbui/lang/de.c A payloads/cbui/lang/en.c A payloads/cbui/lang/lang.c A payloads/cbui/lang/lang.h A payloads/cbui/logo/cbui.png A payloads/cbui/lp.config A payloads/cbui/modules/bootlog_module.c A payloads/cbui/modules/cbfs_module.c A payloads/cbui/modules/cmos_module.c A payloads/cbui/modules/coreboot_module.c A payloads/cbui/modules/cpuinfo_module.c A payloads/cbui/modules/license_module.c A payloads/cbui/modules/modules.c A payloads/cbui/modules/modules.h A payloads/cbui/modules/nvram_module.c A payloads/cbui/modules/pci_module.c A payloads/cbui/modules/reboot_module.c A payloads/cbui/modules/rtc_module.c A payloads/cbui/modules/rw_module.c A payloads/cbui/modules/timestamps_module.c A payloads/cbui/modules/usb_module.c A payloads/libpayload/configs/defconfig-cbui 112 files changed, 17,000 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/23586/164 -- To view, visit https://review.coreboot.org/c/coreboot/+/23586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9a1a07c1065880aa675380625021750d5cab7d1 Gerrit-Change-Number: 23586 Gerrit-PatchSet: 164 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Iman Bingi <imanbingy(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Iman Bingi <imanbingy(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[master]: util/amdfwtool/amdfwread: Handle recovery A/B layout
by Karthik Ramasubramanian (Code Review) 20 Oct '22

20 Oct '22

Attention is currently required from: Robert Zieba, Bao Zheng, Raul Rangel, Jon Murphy, Rob Barnes, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66554 ) Change subject: util/amdfwtool/amdfwread: Handle recovery A/B layout ...................................................................... Patch Set 14: (1 comment) File util/amdfwtool/amdfwread.c: https://review.coreboot.org/c/coreboot/+/66554/comment/cf6cd814_71b1eb39 PS14, Line 157: break > Why the break? Don't we want to validate all the entries in the list? This is the break for the case statement so that we dont fallthrough to the next case. We are still processing all the entries in the list. -- To view, visit https://review.coreboot.org/c/coreboot/+/66554 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6576eaebc611ab338885aed2ee087bf85da3ca15 Gerrit-Change-Number: 66554 Gerrit-PatchSet: 14 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 20 Oct 2022 18:16:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/prodrive/atlas: Disable S3
by Angel Pons (Code Review) 20 Oct '22

20 Oct '22

Attention is currently required from: Christian Walter, Maximilian Brune, Lean Sheng Tan. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68591 ) Change subject: mb/prodrive/atlas: Disable S3 ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/68591 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b28787df9b01683fcd4a1de8267840a80bb4fe6 Gerrit-Change-Number: 68591 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Thu, 20 Oct 2022 18:15:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: purism/librem_cnl: Add Kconfig to enable Mini UART
by 9elements QA (Code Review) 20 Oct '22

20 Oct '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68551 ) Change subject: purism/librem_cnl: Add Kconfig to enable Mini UART ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 14 / 1 / 15 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/128978 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/128977 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/128976 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/128975 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/128974 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/128973 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/128972 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/128971 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/128970 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/128969 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/128967 FAIL: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/128966 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/128965 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/128964 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/128963 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/68551 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38ad5f19da6af5ed286ad3583f34b824a3660916 Gerrit-Change-Number: 68551 Gerrit-PatchSet: 2 Gerrit-Owner: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Thu, 20 Oct 2022 18:10:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: arch/x86: Use 'enum cb_err'
by Elyes Haouas (Code Review) 20 Oct '22

20 Oct '22

Attention is currently required from: Angel Pons. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68369 ) Change subject: arch/x86: Use 'enum cb_err' ...................................................................... Patch Set 1: (1 comment) File src/arch/x86/pirq_routing.c: https://review.coreboot.org/c/coreboot/+/68369/comment/e102e87e_e70b9359 PS1, Line 185: verify_copy_pirq_routing_table(addr, routing_table); > The return value is ignored This is out of scope. -- To view, visit https://review.coreboot.org/c/coreboot/+/68369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38e4b8c6adfaaa45377b2fbe0644285d21841cd1 Gerrit-Change-Number: 68369 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 20 Oct 2022 18:06:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/amd/*/uart: cleanup includes
by Elyes Haouas (Code Review) 20 Oct '22

20 Oct '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68633 ) Change subject: soc/amd/*/uart: cleanup includes ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68633 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I59ab9c2eaa65d974d418123e87e9afe65b1168cc Gerrit-Change-Number: 68633 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 20 Oct 2022 18:01:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: arch/x86/include: Split CPUID access into separate file
by Felix Held (Code Review) 20 Oct '22

20 Oct '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67916 ) Change subject: arch/x86/include: Split CPUID access into separate file ...................................................................... arch/x86/include: Split CPUID access into separate file To allow testing of code that uses CPUID calls, separate the actual calls into a separate header file, This allows the tests to emulate the cpuid access without replacing the rest of the cpu.h definitions. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: Ic5ee29f1fbb6304738f2eb7999cbcfdf8f7d4932 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67916 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jakub Czapiga <jacz(a)semihalf.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/arch/x86/include/arch/cpu.h A src/arch/x86/include/arch/cpuid.h 2 files changed, 131 insertions(+), 103 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Angel Pons: Looks good to me, approved Jakub Czapiga: Looks good to me, approved diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index d3f50bf..3402215 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -4,6 +4,7 @@ #define ARCH_CPU_H #include <types.h> +#include <arch/cpuid.h> /* * EFLAGS bits @@ -26,109 +27,6 @@ #define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */ #define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */ -struct cpuid_result { - uint32_t eax; - uint32_t ebx; - uint32_t ecx; - uint32_t edx; -}; - -/* - * Generic CPUID function - */ -static inline struct cpuid_result cpuid(int op) -{ - struct cpuid_result result; - asm volatile( - "mov %%ebx, %%edi;" - "cpuid;" - "mov %%ebx, %%esi;" - "mov %%edi, %%ebx;" - : "=a" (result.eax), - "=S" (result.ebx), - "=c" (result.ecx), - "=d" (result.edx) - : "0" (op) - : "edi"); - return result; -} - -/* - * Generic Extended CPUID function - */ -static inline struct cpuid_result cpuid_ext(int op, unsigned int ecx) -{ - struct cpuid_result result; - asm volatile( - "mov %%ebx, %%edi;" - "cpuid;" - "mov %%ebx, %%esi;" - "mov %%edi, %%ebx;" - : "=a" (result.eax), - "=S" (result.ebx), - "=c" (result.ecx), - "=d" (result.edx) - : "0" (op), "2" (ecx) - : "edi"); - return result; -} - -/* - * CPUID functions returning a single datum - */ -static inline unsigned int cpuid_eax(unsigned int op) -{ - unsigned int eax; - - __asm__("mov %%ebx, %%edi;" - "cpuid;" - "mov %%edi, %%ebx;" - : "=a" (eax) - : "0" (op) - : "ecx", "edx", "edi"); - return eax; -} - -static inline unsigned int cpuid_ebx(unsigned int op) -{ - unsigned int eax, ebx; - - __asm__("mov %%ebx, %%edi;" - "cpuid;" - "mov %%ebx, %%esi;" - "mov %%edi, %%ebx;" - : "=a" (eax), "=S" (ebx) - : "0" (op) - : "ecx", "edx", "edi"); - return ebx; -} - -static inline unsigned int cpuid_ecx(unsigned int op) -{ - unsigned int eax, ecx; - - __asm__("mov %%ebx, %%edi;" - "cpuid;" - "mov %%edi, %%ebx;" - : "=a" (eax), "=c" (ecx) - : "0" (op) - : "edx", "edi"); - return ecx; -} - -static inline unsigned int cpuid_edx(unsigned int op) -{ - unsigned int eax, edx; - - __asm__("mov %%ebx, %%edi;" - "cpuid;" - "mov %%edi, %%ebx;" - : "=a" (eax), "=d" (edx) - : "0" (op) - : "ecx", "edi"); - return edx; -} - static inline unsigned int cpuid_get_max_func(void) { return cpuid_eax(0); diff --git a/src/arch/x86/include/arch/cpuid.h b/src/arch/x86/include/arch/cpuid.h new file mode 100644 index 0000000..27848a8 --- /dev/null +++ b/src/arch/x86/include/arch/cpuid.h @@ -0,0 +1,111 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef ARCH_CPUID_H +#define ARCH_CPUID_H + +#include <types.h> + +struct cpuid_result { + uint32_t eax; + uint32_t ebx; + uint32_t ecx; + uint32_t edx; +}; + +/* + * Generic CPUID function + */ +static inline struct cpuid_result cpuid(int op) +{ + struct cpuid_result result; + asm volatile( + "mov %%ebx, %%edi;" + "cpuid;" + "mov %%ebx, %%esi;" + "mov %%edi, %%ebx;" + : "=a" (result.eax), + "=S" (result.ebx), + "=c" (result.ecx), + "=d" (result.edx) + : "0" (op) + : "edi"); + return result; +} + +/* + * Generic Extended CPUID function + */ +static inline struct cpuid_result cpuid_ext(int op, unsigned int ecx) +{ + struct cpuid_result result; + asm volatile( + "mov %%ebx, %%edi;" + "cpuid;" + "mov %%ebx, %%esi;" + "mov %%edi, %%ebx;" + : "=a" (result.eax), + "=S" (result.ebx), + "=c" (result.ecx), + "=d" (result.edx) + : "0" (op), "2" (ecx) + : "edi"); + return result; +} + +/* + * CPUID functions returning a single datum + */ +static inline unsigned int cpuid_eax(unsigned int op) +{ + unsigned int eax; + + __asm__("mov %%ebx, %%edi;" + "cpuid;" + "mov %%edi, %%ebx;" + : "=a" (eax) + : "0" (op) + : "ecx", "edx", "edi"); + return eax; +} + +static inline unsigned int cpuid_ebx(unsigned int op) +{ + unsigned int eax, ebx; + + __asm__("mov %%ebx, %%edi;" + "cpuid;" + "mov %%ebx, %%esi;" + "mov %%edi, %%ebx;" + : "=a" (eax), "=S" (ebx) + : "0" (op) + : "ecx", "edx", "edi"); + return ebx; +} + +static inline unsigned int cpuid_ecx(unsigned int op) +{ + unsigned int eax, ecx; + + __asm__("mov %%ebx, %%edi;" + "cpuid;" + "mov %%edi, %%ebx;" + : "=a" (eax), "=c" (ecx) + : "0" (op) + : "edx", "edi"); + return ecx; +} + +static inline unsigned int cpuid_edx(unsigned int op) +{ + unsigned int eax, edx; + + __asm__("mov %%ebx, %%edi;" + "cpuid;" + "mov %%edi, %%ebx;" + : "=a" (eax), "=d" (edx) + : "0" (op) + : "ecx", "edi"); + return edx; +} + +#endif /* ARCH_CPUID_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/67916 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5ee29f1fbb6304738f2eb7999cbcfdf8f7d4932 Gerrit-Change-Number: 67916 Gerrit-PatchSet: 4 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[master]: arch/x86/include: Split CPUID access into separate file
by Felix Held (Code Review) 20 Oct '22

20 Oct '22

Attention is currently required from: Martin L Roth, Jan Dabros, Elyes Haouas. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67916 ) Change subject: arch/x86/include: Split CPUID access into separate file ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/67916 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5ee29f1fbb6304738f2eb7999cbcfdf8f7d4932 Gerrit-Change-Number: 67916 Gerrit-PatchSet: 3 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jan Dabros <jsd(a)semihalf.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 20 Oct 2022 17:54:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: mb/google/kahlee: Fix audio ACPI inclusion
by Felix Held (Code Review) 20 Oct '22

20 Oct '22

Attention is currently required from: Jason Nien, Matt DeVillier, Martin Roth. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68583 ) Change subject: mb/google/kahlee: Fix audio ACPI inclusion ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: checked and this is consistent with the devicetrees of the variants -- To view, visit https://review.coreboot.org/c/coreboot/+/68583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb7df4f8e51495ad3cb40113cd00810fd27dcd00 Gerrit-Change-Number: 68583 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Thu, 20 Oct 2022 17:53:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2022