coreboot-gerrit October 2022

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[S] Change in coreboot[master]: mb/prodrive/atlas: Disable S3
by Maximilian Brune (Code Review) 20 Oct '22

20 Oct '22

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68591 ) Change subject: mb/prodrive/atlas: Disable S3 ...................................................................... mb/prodrive/atlas: Disable S3 The Atlas board has currenlty the problem that suspending the System causes the System to freeze. Therefore disable S3, until the cause is figured out and fixed. Change-Id: I5b28787df9b01683fcd4a1de8267840a80bb4fe6 --- M src/mainboard/prodrive/atlas/Kconfig 1 file changed, 13 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/68591/1 diff --git a/src/mainboard/prodrive/atlas/Kconfig b/src/mainboard/prodrive/atlas/Kconfig index f86db31..5f0a053 100644 --- a/src/mainboard/prodrive/atlas/Kconfig +++ b/src/mainboard/prodrive/atlas/Kconfig @@ -4,7 +4,6 @@ select INTEL_LPSS_UART_FOR_CONSOLE select EC_ACPI select FSP_TYPE_IOT - select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_GMA_HAVE_VBT select MAINBOARD_HAS_TPM2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68591 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b28787df9b01683fcd4a1de8267840a80bb4fe6 Gerrit-Change-Number: 68591 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[master]: soc/amd/*/uart: commonize UART code and MMIO device driver
by Felix Held (Code Review) 20 Oct '22

20 Oct '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68561 ) Change subject: soc/amd/*/uart: commonize UART code and MMIO device driver ...................................................................... soc/amd/*/uart: commonize UART code and MMIO device driver Now that the SoC-specific UART controller data and the common code part are cleanly separated, move the code to the common AMD UART support block folder. The code is identical to the UART code in Cezanne, Mendocino, Morgana and Picasso while Stoneyridge doesn't use the parts related to the MMIO device driver. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Id9429dac44bc02147a839db89d06e8eded7f1af2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68561 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- M src/soc/amd/cezanne/chipset.cb M src/soc/amd/cezanne/uart.c M src/soc/amd/common/block/include/amdblocks/uart.h M src/soc/amd/common/block/uart/Makefile.inc A src/soc/amd/common/block/uart/uart.c D src/soc/amd/common/block/uart/uart_acpi.c M src/soc/amd/mendocino/chipset_mendocino.cb M src/soc/amd/mendocino/chipset_rembrandt.cb M src/soc/amd/mendocino/uart.c M src/soc/amd/morgana/chipset.cb M src/soc/amd/morgana/uart.c M src/soc/amd/picasso/chipset.cb M src/soc/amd/picasso/uart.c M src/soc/amd/stoneyridge/uart.c 14 files changed, 169 insertions(+), 439 deletions(-) Approvals: build bot (Jenkins): Verified Fred Reitberger: Looks good to me, approved diff --git a/src/soc/amd/cezanne/chipset.cb b/src/soc/amd/cezanne/chipset.cb index 2c4ff52..3b6e0d8 100644 --- a/src/soc/amd/cezanne/chipset.cb +++ b/src/soc/amd/cezanne/chipset.cb @@ -111,7 +111,7 @@ device mmio 0xfedc3000 alias i2c_1 off ops soc_amd_i2c_mmio_ops end device mmio 0xfedc4000 alias i2c_2 off ops soc_amd_i2c_mmio_ops end device mmio 0xfedc5000 alias i2c_3 off ops soc_amd_i2c_mmio_ops end - device mmio 0xfedc9000 alias uart_0 off ops cezanne_uart_mmio_ops end - device mmio 0xfedca000 alias uart_1 off ops cezanne_uart_mmio_ops end + device mmio 0xfedc9000 alias uart_0 off ops amd_uart_mmio_ops end + device mmio 0xfedca000 alias uart_1 off ops amd_uart_mmio_ops end device mmio 0xfedd5000 alias emmc off ops amd_emmc_mmio_ops end end diff --git a/src/soc/amd/cezanne/uart.c b/src/soc/amd/cezanne/uart.c index 684786b..3ac7deb 100644 --- a/src/soc/amd/cezanne/uart.c +++ b/src/soc/amd/cezanne/uart.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <amdblocks/aoac.h> #include <amdblocks/gpio.h> #include <amdblocks/uart.h> #include <commonlib/helpers.h> @@ -25,105 +24,13 @@ } }, }; -static const struct soc_uart_ctrlr_info *soc_get_uart_ctrlr_info(size_t *num_ctrlrs) +const struct soc_uart_ctrlr_info *soc_get_uart_ctrlr_info(size_t *num_ctrlrs) { *num_ctrlrs = ARRAY_SIZE(uart_info); return uart_info; } -uintptr_t get_uart_base(unsigned int idx) -{ - size_t num_ctrlrs; - const struct soc_uart_ctrlr_info *ctrlr = soc_get_uart_ctrlr_info(&num_ctrlrs); - - if (idx >= num_ctrlrs) - return 0; - - return ctrlr[idx].base; -} - -static enum cb_err get_uart_idx(uintptr_t base, const struct soc_uart_ctrlr_info *ctrlr, - size_t num_ctrlrs, unsigned int *idx) -{ - unsigned int i; - for (i = 0; i < num_ctrlrs; i++) { - if (base == ctrlr[i].base) { - *idx = i; - return CB_SUCCESS; - } - } - return CB_ERR; -} - -static enum cb_err get_uart_aoac_device(uintptr_t base, unsigned int *aoac_dev) -{ - unsigned int idx; - size_t num_ctrlrs; - const struct soc_uart_ctrlr_info *ctrlr = soc_get_uart_ctrlr_info(&num_ctrlrs); - - if (get_uart_idx(base, ctrlr, num_ctrlrs, &idx) == CB_ERR) - return CB_ERR; - - *aoac_dev = ctrlr[idx].aoac_device; - return CB_SUCCESS; -} - void clear_uart_legacy_config(void) { write16p(FCH_LEGACY_UART_DECODE, 0); } - -void set_uart_config(unsigned int idx) -{ - size_t num_ctrlrs; - const struct soc_uart_ctrlr_info *ctrlr = soc_get_uart_ctrlr_info(&num_ctrlrs); - - if (idx >= num_ctrlrs) - return; - - gpio_configure_pads(ctrlr[idx].mux, 2); -} - -static const char *uart_acpi_name(const struct device *dev) -{ - unsigned int idx; - size_t num_ctrlrs; - const struct soc_uart_ctrlr_info *ctrlr = soc_get_uart_ctrlr_info(&num_ctrlrs); - - if (get_uart_idx(dev->path.mmio.addr, ctrlr, num_ctrlrs, &idx) == CB_SUCCESS) - return ctrlr[idx].acpi_name; - else - return NULL; -} - -/* Even though this is called enable, it gets called for both enabled and disabled devices. */ -static void uart_enable(struct device *dev) -{ - unsigned int dev_id; - - if (get_uart_aoac_device(dev->path.mmio.addr, &dev_id) == CB_ERR) { - printk(BIOS_ERR, "%s: Unknown device: %s\n", __func__, dev_path(dev)); - return; - } - - if (dev->enabled) { - power_on_aoac_device(dev_id); - wait_for_aoac_enabled(dev_id); - } else { - power_off_aoac_device(dev_id); - } -} - -static void uart_read_resources(struct device *dev) -{ - mmio_resource_kb(dev, 0, dev->path.mmio.addr / KiB, 4); -} - -struct device_operations cezanne_uart_mmio_ops = { - .read_resources = uart_read_resources, - .set_resources = noop_set_resources, - .scan_bus = scan_static_bus, - .enable = uart_enable, - .acpi_name = uart_acpi_name, - .acpi_fill_ssdt = uart_inject_ssdt, -}; diff --git a/src/soc/amd/common/block/include/amdblocks/uart.h b/src/soc/amd/common/block/include/amdblocks/uart.h index a613bbe..fbce4e8 100644 --- a/src/soc/amd/common/block/include/amdblocks/uart.h +++ b/src/soc/amd/common/block/include/amdblocks/uart.h @@ -15,7 +15,9 @@ }; uintptr_t get_uart_base(unsigned int idx); /* get MMIO base address of FCH UART */ -void uart_inject_ssdt(const struct device *dev); void set_uart_config(unsigned int idx); /* configure hardware of FCH UART selected by idx */ +/* Getter function to get the SoC UART Controller Information. */ +const struct soc_uart_ctrlr_info *soc_get_uart_ctrlr_info(size_t *num_ctrlrs); + #endif /* AMD_BLOCK_UART_H */ diff --git a/src/soc/amd/common/block/uart/Makefile.inc b/src/soc/amd/common/block/uart/Makefile.inc index 6982fcf..153878c 100644 --- a/src/soc/amd/common/block/uart/Makefile.inc +++ b/src/soc/amd/common/block/uart/Makefile.inc @@ -1,11 +1,17 @@ ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_UART),y) +# all-y can't be used, since verstage on PSP has a different implementation +bootblock-y += uart.c +verstage_x86-y += uart.c +romstage-y += uart.c +postcar-y += uart.c +ramstage-y += uart.c +smm-$(CONFIG_DEBUG_SMI) += uart.c + all-$(CONFIG_AMD_SOC_CONSOLE_UART) += uart_console.c ifeq ($(CONFIG_DEBUG_SMI),y) smm-$(CONFIG_AMD_SOC_CONSOLE_UART) += uart_console.c endif -ramstage-$(CONFIG_HAVE_ACPI_TABLES) += uart_acpi.c - endif # CONFIG_SOC_AMD_COMMON_BLOCK_UART diff --git a/src/soc/amd/common/block/uart/uart.c b/src/soc/amd/common/block/uart/uart.c new file mode 100644 index 0000000..125e780 --- /dev/null +++ b/src/soc/amd/common/block/uart/uart.c @@ -0,0 +1,113 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpigen.h> +#include <amdblocks/aoac.h> +#include <amdblocks/gpio.h> +#include <amdblocks/uart.h> +#include <device/device.h> + +uintptr_t get_uart_base(unsigned int idx) +{ + size_t num_ctrlrs; + const struct soc_uart_ctrlr_info *ctrlr = soc_get_uart_ctrlr_info(&num_ctrlrs); + + if (idx >= num_ctrlrs) + return 0; + + return ctrlr[idx].base; +} + +static enum cb_err get_uart_idx(uintptr_t base, const struct soc_uart_ctrlr_info *ctrlr, + size_t num_ctrlrs, unsigned int *idx) +{ + unsigned int i; + for (i = 0; i < num_ctrlrs; i++) { + if (base == ctrlr[i].base) { + *idx = i; + return CB_SUCCESS; + } + } + return CB_ERR; +} + +static enum cb_err get_uart_aoac_device(uintptr_t base, unsigned int *aoac_dev) +{ + unsigned int idx; + size_t num_ctrlrs; + const struct soc_uart_ctrlr_info *ctrlr = soc_get_uart_ctrlr_info(&num_ctrlrs); + + if (get_uart_idx(base, ctrlr, num_ctrlrs, &idx) == CB_ERR) + return CB_ERR; + + *aoac_dev = ctrlr[idx].aoac_device; + return CB_SUCCESS; +} + +void set_uart_config(unsigned int idx) +{ + size_t num_ctrlrs; + const struct soc_uart_ctrlr_info *ctrlr = soc_get_uart_ctrlr_info(&num_ctrlrs); + + if (idx >= num_ctrlrs) + return; + + gpio_configure_pads(ctrlr[idx].mux, 2); +} + +#if CONFIG(HAVE_ACPI_TABLES) +static const char *uart_acpi_name(const struct device *dev) +{ + unsigned int idx; + size_t num_ctrlrs; + const struct soc_uart_ctrlr_info *ctrlr = soc_get_uart_ctrlr_info(&num_ctrlrs); + + if (get_uart_idx(dev->path.mmio.addr, ctrlr, num_ctrlrs, &idx) == CB_SUCCESS) + return ctrlr[idx].acpi_name; + else + return NULL; +} + +/* This gets called for both enabled and disabled devices. */ +static void uart_inject_ssdt(const struct device *dev) +{ + acpigen_write_scope(acpi_device_path(dev)); + + acpigen_write_STA(acpi_device_status(dev)); + + acpigen_pop_len(); /* Scope */ +} +#endif + +/* Even though this is called enable, it gets called for both enabled and disabled devices. */ +static void uart_enable(struct device *dev) +{ + unsigned int dev_id; + + if (get_uart_aoac_device(dev->path.mmio.addr, &dev_id) == CB_ERR) { + printk(BIOS_ERR, "%s: Unknown device: %s\n", __func__, dev_path(dev)); + return; + } + + if (dev->enabled) { + power_on_aoac_device(dev_id); + wait_for_aoac_enabled(dev_id); + } else { + power_off_aoac_device(dev_id); + } +} + +static void uart_read_resources(struct device *dev) +{ + mmio_resource_kb(dev, 0, dev->path.mmio.addr / KiB, 4); +} + +struct device_operations amd_uart_mmio_ops = { + .read_resources = uart_read_resources, + .set_resources = noop_set_resources, + .scan_bus = scan_static_bus, + .enable = uart_enable, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_name = uart_acpi_name, + .acpi_fill_ssdt = uart_inject_ssdt, +#endif +}; diff --git a/src/soc/amd/common/block/uart/uart_acpi.c b/src/soc/amd/common/block/uart/uart_acpi.c deleted file mode 100644 index eb17322..0000000 --- a/src/soc/amd/common/block/uart/uart_acpi.c +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <acpi/acpigen.h> -#include <amdblocks/uart.h> -#include <device/device.h> - -/* This gets called for both enabled and disabled devices. */ -void uart_inject_ssdt(const struct device *dev) -{ - acpigen_write_scope(acpi_device_path(dev)); - - acpigen_write_STA(acpi_device_status(dev)); - - acpigen_pop_len(); /* Scope */ -} diff --git a/src/soc/amd/mendocino/chipset_mendocino.cb b/src/soc/amd/mendocino/chipset_mendocino.cb index 170b44c..23afdba 100644 --- a/src/soc/amd/mendocino/chipset_mendocino.cb +++ b/src/soc/amd/mendocino/chipset_mendocino.cb @@ -88,10 +88,10 @@ device mmio 0xfedc3000 alias i2c_1 off ops soc_amd_i2c_mmio_ops end device mmio 0xfedc4000 alias i2c_2 off ops soc_amd_i2c_mmio_ops end device mmio 0xfedc5000 alias i2c_3 off ops soc_amd_i2c_mmio_ops end - device mmio 0xfedc9000 alias uart_0 off ops mendocino_uart_mmio_ops end - device mmio 0xfedca000 alias uart_1 off ops mendocino_uart_mmio_ops end - device mmio 0xfedce000 alias uart_2 off ops mendocino_uart_mmio_ops end - device mmio 0xfedcf000 alias uart_3 off ops mendocino_uart_mmio_ops end - device mmio 0xfedd1000 alias uart_4 off ops mendocino_uart_mmio_ops end + device mmio 0xfedc9000 alias uart_0 off ops amd_uart_mmio_ops end + device mmio 0xfedca000 alias uart_1 off ops amd_uart_mmio_ops end + device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end + device mmio 0xfedcf000 alias uart_3 off ops amd_uart_mmio_ops end + device mmio 0xfedd1000 alias uart_4 off ops amd_uart_mmio_ops end device mmio 0xfedd5000 alias emmc off ops amd_emmc_mmio_ops end end diff --git a/src/soc/amd/mendocino/chipset_rembrandt.cb b/src/soc/amd/mendocino/chipset_rembrandt.cb index 170b44c..23afdba 100644 --- a/src/soc/amd/mendocino/chipset_rembrandt.cb +++ b/src/soc/amd/mendocino/chipset_rembrandt.cb @@ -88,10 +88,10 @@ device mmio 0xfedc3000 alias i2c_1 off ops soc_amd_i2c_mmio_ops end device mmio 0xfedc4000 alias i2c_2 off ops soc_amd_i2c_mmio_ops end device mmio 0xfedc5000 alias i2c_3 off ops soc_amd_i2c_mmio_ops end - device mmio 0xfedc9000 alias uart_0 off ops mendocino_uart_mmio_ops end - device mmio 0xfedca000 alias uart_1 off ops mendocino_uart_mmio_ops end - device mmio 0xfedce000 alias uart_2 off ops mendocino_uart_mmio_ops end - device mmio 0xfedcf000 alias uart_3 off ops mendocino_uart_mmio_ops end - device mmio 0xfedd1000 alias uart_4 off ops mendocino_uart_mmio_ops end + device mmio 0xfedc9000 alias uart_0 off ops amd_uart_mmio_ops end + device mmio 0xfedca000 alias uart_1 off ops amd_uart_mmio_ops end + device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end + device mmio 0xfedcf000 alias uart_3 off ops amd_uart_mmio_ops end + device mmio 0xfedd1000 alias uart_4 off ops amd_uart_mmio_ops end device mmio 0xfedd5000 alias emmc off ops amd_emmc_mmio_ops end end diff --git a/src/soc/amd/mendocino/uart.c b/src/soc/amd/mendocino/uart.c index 07e831c..d4bf2fe 100644 --- a/src/soc/amd/mendocino/uart.c +++ b/src/soc/amd/mendocino/uart.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <amdblocks/aoac.h> #include <amdblocks/gpio.h> #include <amdblocks/uart.h> #include <commonlib/helpers.h> @@ -37,105 +36,13 @@ } }, }; -static const struct soc_uart_ctrlr_info *soc_get_uart_ctrlr_info(size_t *num_ctrlrs) +const struct soc_uart_ctrlr_info *soc_get_uart_ctrlr_info(size_t *num_ctrlrs) { *num_ctrlrs = ARRAY_SIZE(uart_info); return uart_info; } -uintptr_t get_uart_base(unsigned int idx) -{ - size_t num_ctrlrs; - const struct soc_uart_ctrlr_info *ctrlr = soc_get_uart_ctrlr_info(&num_ctrlrs); - - if (idx >= num_ctrlrs) - return 0; - - return ctrlr[idx].base; -} - -static enum cb_err get_uart_idx(uintptr_t base, const struct soc_uart_ctrlr_info *ctrlr, - size_t num_ctrlrs, unsigned int *idx) -{ - unsigned int i; - for (i = 0; i < num_ctrlrs; i++) { - if (base == ctrlr[i].base) { - *idx = i; - return CB_SUCCESS; - } - } - return CB_ERR; -} - -static enum cb_err get_uart_aoac_device(uintptr_t base, unsigned int *aoac_dev) -{ - unsigned int idx; - size_t num_ctrlrs; - const struct soc_uart_ctrlr_info *ctrlr = soc_get_uart_ctrlr_info(&num_ctrlrs); - - if (get_uart_idx(base, ctrlr, num_ctrlrs, &idx) == CB_ERR) - return CB_ERR; - - *aoac_dev = ctrlr[idx].aoac_device; - return CB_SUCCESS; -} - void clear_uart_legacy_config(void) { write16p(FCH_LEGACY_UART_DECODE, 0); } - -void set_uart_config(unsigned int idx) -{ - size_t num_ctrlrs; - const struct soc_uart_ctrlr_info *ctrlr = soc_get_uart_ctrlr_info(&num_ctrlrs); - - if (idx >= num_ctrlrs) - return; - - gpio_configure_pads(ctrlr[idx].mux, 2); -} - -static const char *uart_acpi_name(const struct device *dev) -{ - unsigned int idx; - size_t num_ctrlrs; - const struct soc_uart_ctrlr_info *ctrlr = soc_get_uart_ctrlr_info(&num_ctrlrs); - - if (get_uart_idx(dev->path.mmio.addr, ctrlr, num_ctrlrs, &idx) == CB_SUCCESS) - return ctrlr[idx].acpi_name; - else - return NULL; -} - -/* Even though this is called enable, it gets called for both enabled and disabled devices. */ -static void uart_enable(struct device *dev) -{ - unsigned int dev_id; - - if (get_uart_aoac_device(dev->path.mmio.addr, &dev_id) == CB_ERR) { - printk(BIOS_ERR, "%s: Unknown device: %s\n", __func__, dev_path(dev)); - return; - } - - if (dev->enabled) { - power_on_aoac_device(dev_id); - wait_for_aoac_enabled(dev_id); - } else { - power_off_aoac_device(dev_id); - } -} - -static void uart_read_resources(struct device *dev) -{ - mmio_resource_kb(dev, 0, dev->path.mmio.addr / KiB, 4); -} - -struct device_operations mendocino_uart_mmio_ops = { - .read_resources = uart_read_resources, - .set_resources = noop_set_resources, - .scan_bus = scan_static_bus, - .enable = uart_enable, - .acpi_name = uart_acpi_name, - .acpi_fill_ssdt = uart_inject_ssdt, -}; diff --git a/src/soc/amd/morgana/chipset.cb b/src/soc/amd/morgana/chipset.cb index 9407e79..ffea57d 100644 --- a/src/soc/amd/morgana/chipset.cb +++ b/src/soc/amd/morgana/chipset.cb @@ -90,10 +90,10 @@ device mmio 0xfedc3000 alias i2c_1 off ops soc_amd_i2c_mmio_ops end device mmio 0xfedc4000 alias i2c_2 off ops soc_amd_i2c_mmio_ops end device mmio 0xfedc5000 alias i2c_3 off ops soc_amd_i2c_mmio_ops end - device mmio 0xfedc9000 alias uart_0 off ops morgana_uart_mmio_ops end - device mmio 0xfedca000 alias uart_1 off ops morgana_uart_mmio_ops end - device mmio 0xfedce000 alias uart_2 off ops morgana_uart_mmio_ops end - device mmio 0xfedcf000 alias uart_3 off ops morgana_uart_mmio_ops end - device mmio 0xfedd1000 alias uart_4 off ops morgana_uart_mmio_ops end + device mmio 0xfedc9000 alias uart_0 off ops amd_uart_mmio_ops end + device mmio 0xfedca000 alias uart_1 off ops amd_uart_mmio_ops end + device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end + device mmio 0xfedcf000 alias uart_3 off ops amd_uart_mmio_ops end + device mmio 0xfedd1000 alias uart_4 off ops amd_uart_mmio_ops end device mmio 0xfedd5000 alias emmc off ops amd_emmc_mmio_ops end end diff --git a/src/soc/amd/morgana/uart.c b/src/soc/amd/morgana/uart.c index f6c552c..401a134 100644 --- a/src/soc/amd/morgana/uart.c +++ b/src/soc/amd/morgana/uart.c @@ -2,7 +2,6 @@ /* TODO: Update for Morgana */ -#include <amdblocks/aoac.h> #include <amdblocks/gpio.h> #include <amdblocks/uart.h> #include <commonlib/helpers.h> @@ -39,105 +38,13 @@ } }, }; -static const struct soc_uart_ctrlr_info *soc_get_uart_ctrlr_info(size_t *num_ctrlrs) +const struct soc_uart_ctrlr_info *soc_get_uart_ctrlr_info(size_t *num_ctrlrs) { *num_ctrlrs = ARRAY_SIZE(uart_info); return uart_info; } -uintptr_t get_uart_base(unsigned int idx) -{ - size_t num_ctrlrs; - const struct soc_uart_ctrlr_info *ctrlr = soc_get_uart_ctrlr_info(&num_ctrlrs); - - if (idx >= num_ctrlrs) - return 0; - - return ctrlr[idx].base; -} - -static enum cb_err get_uart_idx(uintptr_t base, const struct soc_uart_ctrlr_info *ctrlr, - size_t num_ctrlrs, unsigned int *idx) -{ - unsigned int i; - for (i = 0; i < num_ctrlrs; i++) { - if (base == ctrlr[i].base) { - *idx = i; - return CB_SUCCESS; - } - } - return CB_ERR; -} - -static enum cb_err get_uart_aoac_device(uintptr_t base, unsigned int *aoac_dev) -{ - unsigned int idx; - size_t num_ctrlrs; - const struct soc_uart_ctrlr_info *ctrlr = soc_get_uart_ctrlr_info(&num_ctrlrs); - - if (get_uart_idx(base, ctrlr, num_ctrlrs, &idx) == CB_ERR) - return CB_ERR; - - *aoac_dev = ctrlr[idx].aoac_device; - return CB_SUCCESS; -} - void clear_uart_legacy_config(void) { write16p(FCH_LEGACY_UART_DECODE, 0); } - -void set_uart_config(unsigned int idx) -{ - size_t num_ctrlrs; - const struct soc_uart_ctrlr_info *ctrlr = soc_get_uart_ctrlr_info(&num_ctrlrs); - - if (idx >= num_ctrlrs) - return; - - gpio_configure_pads(ctrlr[idx].mux, 2); -} - -static const char *uart_acpi_name(const struct device *dev) -{ - unsigned int idx; - size_t num_ctrlrs; - const struct soc_uart_ctrlr_info *ctrlr = soc_get_uart_ctrlr_info(&num_ctrlrs); - - if (get_uart_idx(dev->path.mmio.addr, ctrlr, num_ctrlrs, &idx) == CB_SUCCESS) - return ctrlr[idx].acpi_name; - else - return NULL; -} - -/* Even though this is called enable, it gets called for both enabled and disabled devices. */ -static void uart_enable(struct device *dev) -{ - unsigned int dev_id; - - if (get_uart_aoac_device(dev->path.mmio.addr, &dev_id) == CB_ERR) { - printk(BIOS_ERR, "%s: Unknown device: %s\n", __func__, dev_path(dev)); - return; - } - - if (dev->enabled) { - power_on_aoac_device(dev_id); - wait_for_aoac_enabled(dev_id); - } else { - power_off_aoac_device(dev_id); - } -} - -static void uart_read_resources(struct device *dev) -{ - mmio_resource_kb(dev, 0, dev->path.mmio.addr / KiB, 4); -} - -struct device_operations morgana_uart_mmio_ops = { - .read_resources = uart_read_resources, - .set_resources = noop_set_resources, - .scan_bus = scan_static_bus, - .enable = uart_enable, - .acpi_name = uart_acpi_name, - .acpi_fill_ssdt = uart_inject_ssdt, -}; diff --git a/src/soc/amd/picasso/chipset.cb b/src/soc/amd/picasso/chipset.cb index ab286de..e44ca8d 100644 --- a/src/soc/amd/picasso/chipset.cb +++ b/src/soc/amd/picasso/chipset.cb @@ -49,8 +49,8 @@ device mmio 0xfedc4000 alias i2c_2 off ops soc_amd_i2c_mmio_ops end device mmio 0xfedc5000 alias i2c_3 off ops soc_amd_i2c_mmio_ops end - device mmio 0xfedc9000 alias uart_0 off ops picasso_uart_mmio_ops end - device mmio 0xfedca000 alias uart_1 off ops picasso_uart_mmio_ops end - device mmio 0xfedce000 alias uart_2 off ops picasso_uart_mmio_ops end - device mmio 0xfedcf000 alias uart_3 off ops picasso_uart_mmio_ops end + device mmio 0xfedc9000 alias uart_0 off ops amd_uart_mmio_ops end + device mmio 0xfedca000 alias uart_1 off ops amd_uart_mmio_ops end + device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end + device mmio 0xfedcf000 alias uart_3 off ops amd_uart_mmio_ops end end diff --git a/src/soc/amd/picasso/uart.c b/src/soc/amd/picasso/uart.c index 5bb67da..e3e3aa9 100644 --- a/src/soc/amd/picasso/uart.c +++ b/src/soc/amd/picasso/uart.c @@ -5,7 +5,6 @@ #include <device/device.h> #include <device/mmio.h> #include <amdblocks/gpio.h> -#include <amdblocks/aoac.h> #include <amdblocks/uart.h> #include <soc/aoac_defs.h> #include <soc/gpio.h> @@ -33,105 +32,13 @@ } }, }; -static const struct soc_uart_ctrlr_info *soc_get_uart_ctrlr_info(size_t *num_ctrlrs) +const struct soc_uart_ctrlr_info *soc_get_uart_ctrlr_info(size_t *num_ctrlrs) { *num_ctrlrs = ARRAY_SIZE(uart_info); return uart_info; } -uintptr_t get_uart_base(unsigned int idx) -{ - size_t num_ctrlrs; - const struct soc_uart_ctrlr_info *ctrlr = soc_get_uart_ctrlr_info(&num_ctrlrs); - - if (idx >= num_ctrlrs) - return 0; - - return ctrlr[idx].base; -} - -static enum cb_err get_uart_idx(uintptr_t base, const struct soc_uart_ctrlr_info *ctrlr, - size_t num_ctrlrs, unsigned int *idx) -{ - unsigned int i; - for (i = 0; i < num_ctrlrs; i++) { - if (base == ctrlr[i].base) { - *idx = i; - return CB_SUCCESS; - } - } - return CB_ERR; -} - -static enum cb_err get_uart_aoac_device(uintptr_t base, unsigned int *aoac_dev) -{ - unsigned int idx; - size_t num_ctrlrs; - const struct soc_uart_ctrlr_info *ctrlr = soc_get_uart_ctrlr_info(&num_ctrlrs); - - if (get_uart_idx(base, ctrlr, num_ctrlrs, &idx) == CB_ERR) - return CB_ERR; - - *aoac_dev = ctrlr[idx].aoac_device; - return CB_SUCCESS; -} - void clear_uart_legacy_config(void) { write16p(FCH_LEGACY_UART_DECODE, 0); } - -void set_uart_config(unsigned int idx) -{ - size_t num_ctrlrs; - const struct soc_uart_ctrlr_info *ctrlr = soc_get_uart_ctrlr_info(&num_ctrlrs); - - if (idx >= num_ctrlrs) - return; - - gpio_configure_pads(ctrlr[idx].mux, 2); -} - -static const char *uart_acpi_name(const struct device *dev) -{ - unsigned int idx; - size_t num_ctrlrs; - const struct soc_uart_ctrlr_info *ctrlr = soc_get_uart_ctrlr_info(&num_ctrlrs); - - if (get_uart_idx(dev->path.mmio.addr, ctrlr, num_ctrlrs, &idx) == CB_SUCCESS) - return ctrlr[idx].acpi_name; - else - return NULL; -} - -/* Even though this is called enable, it gets called for both enabled and disabled devices. */ -static void uart_enable(struct device *dev) -{ - unsigned int dev_id; - - if (get_uart_aoac_device(dev->path.mmio.addr, &dev_id) == CB_ERR) { - printk(BIOS_ERR, "%s: Unknown device: %s\n", __func__, dev_path(dev)); - return; - } - - if (dev->enabled) { - power_on_aoac_device(dev_id); - wait_for_aoac_enabled(dev_id); - } else { - power_off_aoac_device(dev_id); - } -} - -static void uart_read_resources(struct device *dev) -{ - mmio_resource_kb(dev, 0, dev->path.mmio.addr / KiB, 4); -} - -struct device_operations picasso_uart_mmio_ops = { - .read_resources = uart_read_resources, - .set_resources = noop_set_resources, - .scan_bus = scan_static_bus, - .acpi_name = uart_acpi_name, - .enable = uart_enable, - .acpi_fill_ssdt = uart_inject_ssdt, -}; diff --git a/src/soc/amd/stoneyridge/uart.c b/src/soc/amd/stoneyridge/uart.c index 837a1bf..86e2626 100644 --- a/src/soc/amd/stoneyridge/uart.c +++ b/src/soc/amd/stoneyridge/uart.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <amdblocks/aoac.h> #include <amdblocks/gpio.h> #include <amdblocks/uart.h> #include <soc/aoac_defs.h> @@ -19,30 +18,8 @@ } }, }; -static const struct soc_uart_ctrlr_info *soc_get_uart_ctrlr_info(size_t *num_ctrlrs) +const struct soc_uart_ctrlr_info *soc_get_uart_ctrlr_info(size_t *num_ctrlrs) { *num_ctrlrs = ARRAY_SIZE(uart_info); return uart_info; } - -uintptr_t get_uart_base(unsigned int idx) -{ - size_t num_ctrlrs; - const struct soc_uart_ctrlr_info *ctrlr = soc_get_uart_ctrlr_info(&num_ctrlrs); - - if (idx >= num_ctrlrs) - return 0; - - return ctrlr[idx].base; -} - -void set_uart_config(unsigned int idx) -{ - size_t num_ctrlrs; - const struct soc_uart_ctrlr_info *ctrlr = soc_get_uart_ctrlr_info(&num_ctrlrs); - - if (idx >= num_ctrlrs) - return; - - gpio_configure_pads(ctrlr[idx].mux, 2); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/68561 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9429dac44bc02147a839db89d06e8eded7f1af2 Gerrit-Change-Number: 68561 Gerrit-PatchSet: 7 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: soc/amd: move set_uart_config prototype to common UART header
by Felix Held (Code Review) 20 Oct '22

20 Oct '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68560 ) Change subject: soc/amd: move set_uart_config prototype to common UART header ...................................................................... soc/amd: move set_uart_config prototype to common UART header Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I97860292fd3cd0330fec40edb31089cd6608906b Reviewed-on: https://review.coreboot.org/c/coreboot/+/68560 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- M src/soc/amd/cezanne/early_fch.c M src/soc/amd/cezanne/include/soc/uart.h M src/soc/amd/common/block/include/amdblocks/uart.h M src/soc/amd/mendocino/early_fch.c M src/soc/amd/mendocino/include/soc/uart.h M src/soc/amd/morgana/early_fch.c M src/soc/amd/morgana/include/soc/uart.h M src/soc/amd/picasso/early_fch.c M src/soc/amd/picasso/include/soc/uart.h M src/soc/amd/stoneyridge/early_fch.c M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/uart.c 12 files changed, 19 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Fred Reitberger: Looks good to me, approved diff --git a/src/soc/amd/cezanne/early_fch.c b/src/soc/amd/cezanne/early_fch.c index 0b8e9a0..9e99da2 100644 --- a/src/soc/amd/cezanne/early_fch.c +++ b/src/soc/amd/cezanne/early_fch.c @@ -7,6 +7,7 @@ #include <amdblocks/lpc.h> #include <amdblocks/pmlib.h> #include <amdblocks/smbus.h> +#include <amdblocks/uart.h> #include <soc/i2c.h> #include <soc/southbridge.h> #include <soc/uart.h> diff --git a/src/soc/amd/cezanne/include/soc/uart.h b/src/soc/amd/cezanne/include/soc/uart.h index 8affe10..b9242d7 100644 --- a/src/soc/amd/cezanne/include/soc/uart.h +++ b/src/soc/amd/cezanne/include/soc/uart.h @@ -5,7 +5,6 @@ #include <types.h> -void set_uart_config(unsigned int idx); /* configure hardware of FCH UART selected by idx */ void clear_uart_legacy_config(void); /* disable legacy I/O decode for FCH UART */ #endif /* AMD_CEZANNE_UART_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/uart.h b/src/soc/amd/common/block/include/amdblocks/uart.h index 4e8ea8c..a613bbe 100644 --- a/src/soc/amd/common/block/include/amdblocks/uart.h +++ b/src/soc/amd/common/block/include/amdblocks/uart.h @@ -16,5 +16,6 @@ uintptr_t get_uart_base(unsigned int idx); /* get MMIO base address of FCH UART */ void uart_inject_ssdt(const struct device *dev); +void set_uart_config(unsigned int idx); /* configure hardware of FCH UART selected by idx */ #endif /* AMD_BLOCK_UART_H */ diff --git a/src/soc/amd/mendocino/early_fch.c b/src/soc/amd/mendocino/early_fch.c index a1cf908..fb359b3 100644 --- a/src/soc/amd/mendocino/early_fch.c +++ b/src/soc/amd/mendocino/early_fch.c @@ -9,6 +9,7 @@ #include <amdblocks/lpc.h> #include <amdblocks/pmlib.h> #include <amdblocks/smbus.h> +#include <amdblocks/uart.h> #include <soc/i2c.h> #include <soc/southbridge.h> #include <soc/uart.h> diff --git a/src/soc/amd/mendocino/include/soc/uart.h b/src/soc/amd/mendocino/include/soc/uart.h index 6e22ef7..b7bd977 100644 --- a/src/soc/amd/mendocino/include/soc/uart.h +++ b/src/soc/amd/mendocino/include/soc/uart.h @@ -5,7 +5,6 @@ #include <types.h> -void set_uart_config(unsigned int idx); /* configure hardware of FCH UART selected by idx */ void clear_uart_legacy_config(void); /* disable legacy I/O decode for FCH UART */ #endif /* AMD_MENDOCINO_UART_H */ diff --git a/src/soc/amd/morgana/early_fch.c b/src/soc/amd/morgana/early_fch.c index f940dea..f8954b5 100644 --- a/src/soc/amd/morgana/early_fch.c +++ b/src/soc/amd/morgana/early_fch.c @@ -9,6 +9,7 @@ #include <amdblocks/lpc.h> #include <amdblocks/pmlib.h> #include <amdblocks/smbus.h> +#include <amdblocks/uart.h> #include <soc/i2c.h> #include <soc/southbridge.h> #include <soc/uart.h> diff --git a/src/soc/amd/morgana/include/soc/uart.h b/src/soc/amd/morgana/include/soc/uart.h index 45e0ed9..ef911b5 100644 --- a/src/soc/amd/morgana/include/soc/uart.h +++ b/src/soc/amd/morgana/include/soc/uart.h @@ -7,7 +7,6 @@ #include <types.h> -void set_uart_config(unsigned int idx); /* configure hardware of FCH UART selected by idx */ void clear_uart_legacy_config(void); /* disable legacy I/O decode for FCH UART */ #endif /* AMD_MORGANA_UART_H */ diff --git a/src/soc/amd/picasso/early_fch.c b/src/soc/amd/picasso/early_fch.c index e77f296..9716d13 100644 --- a/src/soc/amd/picasso/early_fch.c +++ b/src/soc/amd/picasso/early_fch.c @@ -8,6 +8,7 @@ #include <amdblocks/pmlib.h> #include <amdblocks/smbus.h> #include <amdblocks/spi.h> +#include <amdblocks/uart.h> #include <soc/i2c.h> #include <soc/southbridge.h> #include <soc/uart.h> diff --git a/src/soc/amd/picasso/include/soc/uart.h b/src/soc/amd/picasso/include/soc/uart.h index 9b99cd4..cdcfead 100644 --- a/src/soc/amd/picasso/include/soc/uart.h +++ b/src/soc/amd/picasso/include/soc/uart.h @@ -5,7 +5,6 @@ #include <types.h> -void set_uart_config(unsigned int idx); /* configure hardware of FCH UART selected by idx */ void clear_uart_legacy_config(void); /* disable legacy I/O decode for FCH UART */ #endif /* AMD_PICASSO_UART_H */ diff --git a/src/soc/amd/stoneyridge/early_fch.c b/src/soc/amd/stoneyridge/early_fch.c index 5e2be61..4cc4729 100644 --- a/src/soc/amd/stoneyridge/early_fch.c +++ b/src/soc/amd/stoneyridge/early_fch.c @@ -8,6 +8,7 @@ #include <amdblocks/reset.h> #include <amdblocks/smbus.h> #include <amdblocks/spi.h> +#include <amdblocks/uart.h> #include <soc/southbridge.h> #include <types.h> diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 26500ef..616a6af 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -183,8 +183,6 @@ void fch_clk_output_48Mhz(u32 osc); -void set_uart_config(unsigned int idx); - /* * Call the mainboard to get the USB Over Current Map. The mainboard * returns the map and 0 on Success or -1 on error or no map. There is diff --git a/src/soc/amd/stoneyridge/uart.c b/src/soc/amd/stoneyridge/uart.c index 9a8add0..837a1bf 100644 --- a/src/soc/amd/stoneyridge/uart.c +++ b/src/soc/amd/stoneyridge/uart.c @@ -6,7 +6,6 @@ #include <soc/aoac_defs.h> #include <soc/gpio.h> #include <soc/iomap.h> -#include <soc/southbridge.h> #include <types.h> static const struct soc_uart_ctrlr_info uart_info[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/68560 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97860292fd3cd0330fec40edb31089cd6608906b Gerrit-Change-Number: 68560 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: soc/amd: move all AOAC function prototypes to amdblocks/aoac.h
by Felix Held (Code Review) 20 Oct '22

20 Oct '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68559 ) Change subject: soc/amd: move all AOAC function prototypes to amdblocks/aoac.h ...................................................................... soc/amd: move all AOAC function prototypes to amdblocks/aoac.h Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I3deae150cd1e20fff6507a0f0ba6a375fca430e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68559 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- M src/soc/amd/cezanne/early_fch.c M src/soc/amd/cezanne/include/soc/southbridge.h M src/soc/amd/common/block/include/amdblocks/aoac.h M src/soc/amd/common/psp_verstage/fch.c M src/soc/amd/mendocino/early_fch.c M src/soc/amd/mendocino/include/soc/southbridge.h M src/soc/amd/morgana/early_fch.c M src/soc/amd/morgana/include/soc/southbridge.h M src/soc/amd/picasso/early_fch.c M src/soc/amd/picasso/include/soc/southbridge.h M src/soc/amd/stoneyridge/early_fch.c M src/soc/amd/stoneyridge/include/soc/southbridge.h 12 files changed, 22 insertions(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified Fred Reitberger: Looks good to me, approved diff --git a/src/soc/amd/cezanne/early_fch.c b/src/soc/amd/cezanne/early_fch.c index 4935f66..0b8e9a0 100644 --- a/src/soc/amd/cezanne/early_fch.c +++ b/src/soc/amd/cezanne/early_fch.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/acpimmio.h> +#include <amdblocks/aoac.h> #include <amdblocks/espi.h> #include <amdblocks/i2c.h> #include <amdblocks/lpc.h> diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h index 4e44b89..4cd53cb 100644 --- a/src/soc/amd/cezanne/include/soc/southbridge.h +++ b/src/soc/amd/cezanne/include/soc/southbridge.h @@ -118,7 +118,4 @@ void fch_init(void *chip_info); void fch_final(void *chip_info); -void enable_aoac_devices(void); -void wait_for_aoac_enabled(unsigned int dev); - #endif /* AMD_CEZANNE_SOUTHBRIDGE_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/aoac.h b/src/soc/amd/common/block/include/amdblocks/aoac.h index 455f32d..3944e2e 100644 --- a/src/soc/amd/common/block/include/amdblocks/aoac.h +++ b/src/soc/amd/common/block/include/amdblocks/aoac.h @@ -35,5 +35,8 @@ bool is_aoac_device_enabled(unsigned int dev); void power_on_aoac_device(unsigned int dev); void power_off_aoac_device(unsigned int dev); +/* the following 2 functions are implemented in the SoC code */ +void enable_aoac_devices(void); +void wait_for_aoac_enabled(unsigned int dev); #endif /* AMD_BLOCK_AOAC_H */ diff --git a/src/soc/amd/common/psp_verstage/fch.c b/src/soc/amd/common/psp_verstage/fch.c index d4dcd21..7f850fd 100644 --- a/src/soc/amd/common/psp_verstage/fch.c +++ b/src/soc/amd/common/psp_verstage/fch.c @@ -3,6 +3,7 @@ #include "psp_verstage.h" #include <amdblocks/acpimmio.h> +#include <amdblocks/aoac.h> #include <amdblocks/espi.h> #include <amdblocks/i2c.h> #include <amdblocks/spi.h> diff --git a/src/soc/amd/mendocino/early_fch.c b/src/soc/amd/mendocino/early_fch.c index 3331737..a1cf908 100644 --- a/src/soc/amd/mendocino/early_fch.c +++ b/src/soc/amd/mendocino/early_fch.c @@ -3,6 +3,7 @@ /* TODO: Check if this is still correct */ #include <amdblocks/acpimmio.h> +#include <amdblocks/aoac.h> #include <amdblocks/espi.h> #include <amdblocks/i2c.h> #include <amdblocks/lpc.h> diff --git a/src/soc/amd/mendocino/include/soc/southbridge.h b/src/soc/amd/mendocino/include/soc/southbridge.h index a5a1be4..52c2606 100644 --- a/src/soc/amd/mendocino/include/soc/southbridge.h +++ b/src/soc/amd/mendocino/include/soc/southbridge.h @@ -121,7 +121,4 @@ void fch_init(void *chip_info); void fch_final(void *chip_info); -void enable_aoac_devices(void); -void wait_for_aoac_enabled(unsigned int dev); - #endif /* AMD_MENDOCINO_SOUTHBRIDGE_H */ diff --git a/src/soc/amd/morgana/early_fch.c b/src/soc/amd/morgana/early_fch.c index 1ec7105..f940dea 100644 --- a/src/soc/amd/morgana/early_fch.c +++ b/src/soc/amd/morgana/early_fch.c @@ -3,6 +3,7 @@ /* TODO: Update for Morgana */ #include <amdblocks/acpimmio.h> +#include <amdblocks/aoac.h> #include <amdblocks/espi.h> #include <amdblocks/i2c.h> #include <amdblocks/lpc.h> diff --git a/src/soc/amd/morgana/include/soc/southbridge.h b/src/soc/amd/morgana/include/soc/southbridge.h index 75f0beb..216bf42 100644 --- a/src/soc/amd/morgana/include/soc/southbridge.h +++ b/src/soc/amd/morgana/include/soc/southbridge.h @@ -121,7 +121,4 @@ void fch_init(void *chip_info); void fch_final(void *chip_info); -void enable_aoac_devices(void); -void wait_for_aoac_enabled(unsigned int dev); - #endif /* AMD_MORGANA_SOUTHBRIDGE_H */ diff --git a/src/soc/amd/picasso/early_fch.c b/src/soc/amd/picasso/early_fch.c index f5d392c..e77f296 100644 --- a/src/soc/amd/picasso/early_fch.c +++ b/src/soc/amd/picasso/early_fch.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/acpimmio.h> +#include <amdblocks/aoac.h> #include <amdblocks/espi.h> #include <amdblocks/i2c.h> #include <amdblocks/lpc.h> diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index b8dd67b..a3fb1a2 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -107,7 +107,4 @@ void fch_init(void *chip_info); void fch_final(void *chip_info); -void enable_aoac_devices(void); -void wait_for_aoac_enabled(unsigned int dev); - #endif /* AMD_PICASSO_SOUTHBRIDGE_H */ diff --git a/src/soc/amd/stoneyridge/early_fch.c b/src/soc/amd/stoneyridge/early_fch.c index 763e3f2..5e2be61 100644 --- a/src/soc/amd/stoneyridge/early_fch.c +++ b/src/soc/amd/stoneyridge/early_fch.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/acpimmio.h> +#include <amdblocks/aoac.h> #include <amdblocks/i2c.h> #include <amdblocks/lpc.h> #include <amdblocks/pmlib.h> diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 32c102c..26500ef 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -181,7 +181,6 @@ void fch_init(void *chip_info); void fch_final(void *chip_info); -void enable_aoac_devices(void); void fch_clk_output_48Mhz(u32 osc); void set_uart_config(unsigned int idx); -- To view, visit https://review.coreboot.org/c/coreboot/+/68559 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3deae150cd1e20fff6507a0f0ba6a375fca430e5 Gerrit-Change-Number: 68559 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/stoneyridge/uart: introduce and use soc_get_uart_ctrlr_info
by Felix Held (Code Review) 20 Oct '22

20 Oct '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68538 ) Change subject: soc/amd/stoneyridge/uart: introduce and use soc_get_uart_ctrlr_info ...................................................................... soc/amd/stoneyridge/uart: introduce and use soc_get_uart_ctrlr_info Introduce and use soc_get_uart_ctrlr_info to access the uart_info array to further decouple uart_info from the code as preparation to factor out most of the code to a common implementation. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I813483bc0421043dc67c523f0ea2016a16a29f60 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68538 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- M src/soc/amd/stoneyridge/uart.c 1 file changed, 33 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Fred Reitberger: Looks good to me, approved diff --git a/src/soc/amd/stoneyridge/uart.c b/src/soc/amd/stoneyridge/uart.c index 3b6d49c..9a8add0 100644 --- a/src/soc/amd/stoneyridge/uart.c +++ b/src/soc/amd/stoneyridge/uart.c @@ -20,18 +20,30 @@ } }, }; +static const struct soc_uart_ctrlr_info *soc_get_uart_ctrlr_info(size_t *num_ctrlrs) +{ + *num_ctrlrs = ARRAY_SIZE(uart_info); + return uart_info; +} + uintptr_t get_uart_base(unsigned int idx) { - if (idx >= ARRAY_SIZE(uart_info)) + size_t num_ctrlrs; + const struct soc_uart_ctrlr_info *ctrlr = soc_get_uart_ctrlr_info(&num_ctrlrs); + + if (idx >= num_ctrlrs) return 0; - return uart_info[idx].base; + return ctrlr[idx].base; } void set_uart_config(unsigned int idx) { - if (idx >= ARRAY_SIZE(uart_info)) + size_t num_ctrlrs; + const struct soc_uart_ctrlr_info *ctrlr = soc_get_uart_ctrlr_info(&num_ctrlrs); + + if (idx >= num_ctrlrs) return; - gpio_configure_pads(uart_info[idx].mux, 2); + gpio_configure_pads(ctrlr[idx].mux, 2); } -- To view, visit https://review.coreboot.org/c/coreboot/+/68538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I813483bc0421043dc67c523f0ea2016a16a29f60 Gerrit-Change-Number: 68538 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[master]: soc/amd/morgana/uart: introduce and use soc_get_uart_ctrlr_info
by Felix Held (Code Review) 20 Oct '22

20 Oct '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68537 ) Change subject: soc/amd/morgana/uart: introduce and use soc_get_uart_ctrlr_info ...................................................................... soc/amd/morgana/uart: introduce and use soc_get_uart_ctrlr_info Introduce and use soc_get_uart_ctrlr_info to access the uart_info array to further decouple uart_info from the code as preparation to factor out most of the code to a common implementation. In order to slightly reduce the number of function calls, pass the size of and pointer to uart_info to get_uart_idx as a parameter instead of calling again soc_get_uart_ctrlr_info in get_uart_idx despite all callers already having the information form the soc_get_uart_ctrlr_info call. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I80278f1a098b389d78f8e9a9fb875c4e466dc5db Reviewed-on: https://review.coreboot.org/c/coreboot/+/68537 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- M src/soc/amd/morgana/uart.c 1 file changed, 54 insertions(+), 14 deletions(-) Approvals: build bot (Jenkins): Verified Fred Reitberger: Looks good to me, approved diff --git a/src/soc/amd/morgana/uart.c b/src/soc/amd/morgana/uart.c index 8a77c87..f6c552c 100644 --- a/src/soc/amd/morgana/uart.c +++ b/src/soc/amd/morgana/uart.c @@ -39,19 +39,29 @@ } }, }; -uintptr_t get_uart_base(unsigned int idx) +static const struct soc_uart_ctrlr_info *soc_get_uart_ctrlr_info(size_t *num_ctrlrs) { - if (idx >= ARRAY_SIZE(uart_info)) - return 0; - - return uart_info[idx].base; + *num_ctrlrs = ARRAY_SIZE(uart_info); + return uart_info; } -static enum cb_err get_uart_idx(uintptr_t base, unsigned int *idx) +uintptr_t get_uart_base(unsigned int idx) +{ + size_t num_ctrlrs; + const struct soc_uart_ctrlr_info *ctrlr = soc_get_uart_ctrlr_info(&num_ctrlrs); + + if (idx >= num_ctrlrs) + return 0; + + return ctrlr[idx].base; +} + +static enum cb_err get_uart_idx(uintptr_t base, const struct soc_uart_ctrlr_info *ctrlr, + size_t num_ctrlrs, unsigned int *idx) { unsigned int i; - for (i = 0; i < ARRAY_SIZE(uart_info); i++) { - if (base == uart_info[i].base) { + for (i = 0; i < num_ctrlrs; i++) { + if (base == ctrlr[i].base) { *idx = i; return CB_SUCCESS; } @@ -62,10 +72,13 @@ static enum cb_err get_uart_aoac_device(uintptr_t base, unsigned int *aoac_dev) { unsigned int idx; - if (get_uart_idx(base, &idx) == CB_ERR) + size_t num_ctrlrs; + const struct soc_uart_ctrlr_info *ctrlr = soc_get_uart_ctrlr_info(&num_ctrlrs); + + if (get_uart_idx(base, ctrlr, num_ctrlrs, &idx) == CB_ERR) return CB_ERR; - *aoac_dev = uart_info[idx].aoac_device; + *aoac_dev = ctrlr[idx].aoac_device; return CB_SUCCESS; } @@ -76,17 +89,23 @@ void set_uart_config(unsigned int idx) { - if (idx >= ARRAY_SIZE(uart_info)) + size_t num_ctrlrs; + const struct soc_uart_ctrlr_info *ctrlr = soc_get_uart_ctrlr_info(&num_ctrlrs); + + if (idx >= num_ctrlrs) return; - gpio_configure_pads(uart_info[idx].mux, 2); + gpio_configure_pads(ctrlr[idx].mux, 2); } static const char *uart_acpi_name(const struct device *dev) { unsigned int idx; - if (get_uart_idx(dev->path.mmio.addr, &idx) == CB_SUCCESS) - return uart_info[idx].acpi_name; + size_t num_ctrlrs; + const struct soc_uart_ctrlr_info *ctrlr = soc_get_uart_ctrlr_info(&num_ctrlrs); + + if (get_uart_idx(dev->path.mmio.addr, ctrlr, num_ctrlrs, &idx) == CB_SUCCESS) + return ctrlr[idx].acpi_name; else return NULL; } -- To view, visit https://review.coreboot.org/c/coreboot/+/68537 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80278f1a098b389d78f8e9a9fb875c4e466dc5db Gerrit-Change-Number: 68537 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[master]: soc/amd/mendocino/uart: introduce and use soc_get_uart_ctrlr_info
by Felix Held (Code Review) 20 Oct '22

20 Oct '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68536 ) Change subject: soc/amd/mendocino/uart: introduce and use soc_get_uart_ctrlr_info ...................................................................... soc/amd/mendocino/uart: introduce and use soc_get_uart_ctrlr_info Introduce and use soc_get_uart_ctrlr_info to access the uart_info array to further decouple uart_info from the code as preparation to factor out most of the code to a common implementation. In order to slightly reduce the number of function calls, pass the size of and pointer to uart_info to get_uart_idx as a parameter instead of calling again soc_get_uart_ctrlr_info in get_uart_idx despite all callers already having the information form the soc_get_uart_ctrlr_info call. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I8cfea274f4c9e908c11429199479aec037a00097 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68536 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- M src/soc/amd/mendocino/uart.c 1 file changed, 54 insertions(+), 14 deletions(-) Approvals: build bot (Jenkins): Verified Fred Reitberger: Looks good to me, approved diff --git a/src/soc/amd/mendocino/uart.c b/src/soc/amd/mendocino/uart.c index 3b1cf6d..07e831c 100644 --- a/src/soc/amd/mendocino/uart.c +++ b/src/soc/amd/mendocino/uart.c @@ -37,19 +37,29 @@ } }, }; -uintptr_t get_uart_base(unsigned int idx) +static const struct soc_uart_ctrlr_info *soc_get_uart_ctrlr_info(size_t *num_ctrlrs) { - if (idx >= ARRAY_SIZE(uart_info)) - return 0; - - return uart_info[idx].base; + *num_ctrlrs = ARRAY_SIZE(uart_info); + return uart_info; } -static enum cb_err get_uart_idx(uintptr_t base, unsigned int *idx) +uintptr_t get_uart_base(unsigned int idx) +{ + size_t num_ctrlrs; + const struct soc_uart_ctrlr_info *ctrlr = soc_get_uart_ctrlr_info(&num_ctrlrs); + + if (idx >= num_ctrlrs) + return 0; + + return ctrlr[idx].base; +} + +static enum cb_err get_uart_idx(uintptr_t base, const struct soc_uart_ctrlr_info *ctrlr, + size_t num_ctrlrs, unsigned int *idx) { unsigned int i; - for (i = 0; i < ARRAY_SIZE(uart_info); i++) { - if (base == uart_info[i].base) { + for (i = 0; i < num_ctrlrs; i++) { + if (base == ctrlr[i].base) { *idx = i; return CB_SUCCESS; } @@ -60,10 +70,13 @@ static enum cb_err get_uart_aoac_device(uintptr_t base, unsigned int *aoac_dev) { unsigned int idx; - if (get_uart_idx(base, &idx) == CB_ERR) + size_t num_ctrlrs; + const struct soc_uart_ctrlr_info *ctrlr = soc_get_uart_ctrlr_info(&num_ctrlrs); + + if (get_uart_idx(base, ctrlr, num_ctrlrs, &idx) == CB_ERR) return CB_ERR; - *aoac_dev = uart_info[idx].aoac_device; + *aoac_dev = ctrlr[idx].aoac_device; return CB_SUCCESS; } @@ -74,17 +87,23 @@ void set_uart_config(unsigned int idx) { - if (idx >= ARRAY_SIZE(uart_info)) + size_t num_ctrlrs; + const struct soc_uart_ctrlr_info *ctrlr = soc_get_uart_ctrlr_info(&num_ctrlrs); + + if (idx >= num_ctrlrs) return; - gpio_configure_pads(uart_info[idx].mux, 2); + gpio_configure_pads(ctrlr[idx].mux, 2); } static const char *uart_acpi_name(const struct device *dev) { unsigned int idx; - if (get_uart_idx(dev->path.mmio.addr, &idx) == CB_SUCCESS) - return uart_info[idx].acpi_name; + size_t num_ctrlrs; + const struct soc_uart_ctrlr_info *ctrlr = soc_get_uart_ctrlr_info(&num_ctrlrs); + + if (get_uart_idx(dev->path.mmio.addr, ctrlr, num_ctrlrs, &idx) == CB_SUCCESS) + return ctrlr[idx].acpi_name; else return NULL; } -- To view, visit https://review.coreboot.org/c/coreboot/+/68536 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8cfea274f4c9e908c11429199479aec037a00097 Gerrit-Change-Number: 68536 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/amd/cezanne/uart: introduce and use soc_get_uart_ctrlr_info
by Felix Held (Code Review) 20 Oct '22

20 Oct '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68535 ) Change subject: soc/amd/cezanne/uart: introduce and use soc_get_uart_ctrlr_info ...................................................................... soc/amd/cezanne/uart: introduce and use soc_get_uart_ctrlr_info Introduce and use soc_get_uart_ctrlr_info to access the uart_info array to further decouple uart_info from the code as preparation to factor out most of the code to a common implementation. In order to slightly reduce the number of function calls, pass the size of and pointer to uart_info to get_uart_idx as a parameter instead of calling again soc_get_uart_ctrlr_info in get_uart_idx despite all callers already having the information form the soc_get_uart_ctrlr_info call. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Iab1aec44c55570aa8085aeaf68ec69fe6de0f2ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/68535 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- M src/soc/amd/cezanne/uart.c 1 file changed, 54 insertions(+), 14 deletions(-) Approvals: build bot (Jenkins): Verified Fred Reitberger: Looks good to me, approved diff --git a/src/soc/amd/cezanne/uart.c b/src/soc/amd/cezanne/uart.c index a0edf59..684786b 100644 --- a/src/soc/amd/cezanne/uart.c +++ b/src/soc/amd/cezanne/uart.c @@ -25,19 +25,29 @@ } }, }; -uintptr_t get_uart_base(unsigned int idx) +static const struct soc_uart_ctrlr_info *soc_get_uart_ctrlr_info(size_t *num_ctrlrs) { - if (idx >= ARRAY_SIZE(uart_info)) - return 0; - - return uart_info[idx].base; + *num_ctrlrs = ARRAY_SIZE(uart_info); + return uart_info; } -static enum cb_err get_uart_idx(uintptr_t base, unsigned int *idx) +uintptr_t get_uart_base(unsigned int idx) +{ + size_t num_ctrlrs; + const struct soc_uart_ctrlr_info *ctrlr = soc_get_uart_ctrlr_info(&num_ctrlrs); + + if (idx >= num_ctrlrs) + return 0; + + return ctrlr[idx].base; +} + +static enum cb_err get_uart_idx(uintptr_t base, const struct soc_uart_ctrlr_info *ctrlr, + size_t num_ctrlrs, unsigned int *idx) { unsigned int i; - for (i = 0; i < ARRAY_SIZE(uart_info); i++) { - if (base == uart_info[i].base) { + for (i = 0; i < num_ctrlrs; i++) { + if (base == ctrlr[i].base) { *idx = i; return CB_SUCCESS; } @@ -48,10 +58,13 @@ static enum cb_err get_uart_aoac_device(uintptr_t base, unsigned int *aoac_dev) { unsigned int idx; - if (get_uart_idx(base, &idx) == CB_ERR) + size_t num_ctrlrs; + const struct soc_uart_ctrlr_info *ctrlr = soc_get_uart_ctrlr_info(&num_ctrlrs); + + if (get_uart_idx(base, ctrlr, num_ctrlrs, &idx) == CB_ERR) return CB_ERR; - *aoac_dev = uart_info[idx].aoac_device; + *aoac_dev = ctrlr[idx].aoac_device; return CB_SUCCESS; } @@ -62,17 +75,23 @@ void set_uart_config(unsigned int idx) { - if (idx >= ARRAY_SIZE(uart_info)) + size_t num_ctrlrs; + const struct soc_uart_ctrlr_info *ctrlr = soc_get_uart_ctrlr_info(&num_ctrlrs); + + if (idx >= num_ctrlrs) return; - gpio_configure_pads(uart_info[idx].mux, 2); + gpio_configure_pads(ctrlr[idx].mux, 2); } static const char *uart_acpi_name(const struct device *dev) { unsigned int idx; - if (get_uart_idx(dev->path.mmio.addr, &idx) == CB_SUCCESS) - return uart_info[idx].acpi_name; + size_t num_ctrlrs; + const struct soc_uart_ctrlr_info *ctrlr = soc_get_uart_ctrlr_info(&num_ctrlrs); + + if (get_uart_idx(dev->path.mmio.addr, ctrlr, num_ctrlrs, &idx) == CB_SUCCESS) + return ctrlr[idx].acpi_name; else return NULL; } -- To view, visit https://review.coreboot.org/c/coreboot/+/68535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab1aec44c55570aa8085aeaf68ec69fe6de0f2ba Gerrit-Change-Number: 68535 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/amd/picasso/uart: introduce and use soc_get_uart_ctrlr_info
by Felix Held (Code Review) 20 Oct '22

20 Oct '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68534 ) Change subject: soc/amd/picasso/uart: introduce and use soc_get_uart_ctrlr_info ...................................................................... soc/amd/picasso/uart: introduce and use soc_get_uart_ctrlr_info Introduce and use soc_get_uart_ctrlr_info to access the uart_info array to further decouple uart_info from the code as preparation to factor out most of the code to a common implementation. In order to slightly reduce the number of function calls, pass the size of and pointer to uart_info to get_uart_idx as a parameter instead of calling again soc_get_uart_ctrlr_info in get_uart_idx despite all callers already having the information form the soc_get_uart_ctrlr_info call. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I474e47059eaebcf0b9b77f66ee993f1963ebee77 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68534 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- M src/soc/amd/picasso/uart.c 1 file changed, 54 insertions(+), 14 deletions(-) Approvals: build bot (Jenkins): Verified Fred Reitberger: Looks good to me, approved diff --git a/src/soc/amd/picasso/uart.c b/src/soc/amd/picasso/uart.c index 327cce8..5bb67da 100644 --- a/src/soc/amd/picasso/uart.c +++ b/src/soc/amd/picasso/uart.c @@ -33,19 +33,29 @@ } }, }; -uintptr_t get_uart_base(unsigned int idx) +static const struct soc_uart_ctrlr_info *soc_get_uart_ctrlr_info(size_t *num_ctrlrs) { - if (idx >= ARRAY_SIZE(uart_info)) - return 0; - - return uart_info[idx].base; + *num_ctrlrs = ARRAY_SIZE(uart_info); + return uart_info; } -static enum cb_err get_uart_idx(uintptr_t base, unsigned int *idx) +uintptr_t get_uart_base(unsigned int idx) +{ + size_t num_ctrlrs; + const struct soc_uart_ctrlr_info *ctrlr = soc_get_uart_ctrlr_info(&num_ctrlrs); + + if (idx >= num_ctrlrs) + return 0; + + return ctrlr[idx].base; +} + +static enum cb_err get_uart_idx(uintptr_t base, const struct soc_uart_ctrlr_info *ctrlr, + size_t num_ctrlrs, unsigned int *idx) { unsigned int i; - for (i = 0; i < ARRAY_SIZE(uart_info); i++) { - if (base == uart_info[i].base) { + for (i = 0; i < num_ctrlrs; i++) { + if (base == ctrlr[i].base) { *idx = i; return CB_SUCCESS; } @@ -56,10 +66,13 @@ static enum cb_err get_uart_aoac_device(uintptr_t base, unsigned int *aoac_dev) { unsigned int idx; - if (get_uart_idx(base, &idx) == CB_ERR) + size_t num_ctrlrs; + const struct soc_uart_ctrlr_info *ctrlr = soc_get_uart_ctrlr_info(&num_ctrlrs); + + if (get_uart_idx(base, ctrlr, num_ctrlrs, &idx) == CB_ERR) return CB_ERR; - *aoac_dev = uart_info[idx].aoac_device; + *aoac_dev = ctrlr[idx].aoac_device; return CB_SUCCESS; } @@ -70,17 +83,23 @@ void set_uart_config(unsigned int idx) { - if (idx >= ARRAY_SIZE(uart_info)) + size_t num_ctrlrs; + const struct soc_uart_ctrlr_info *ctrlr = soc_get_uart_ctrlr_info(&num_ctrlrs); + + if (idx >= num_ctrlrs) return; - gpio_configure_pads(uart_info[idx].mux, 2); + gpio_configure_pads(ctrlr[idx].mux, 2); } static const char *uart_acpi_name(const struct device *dev) { unsigned int idx; - if (get_uart_idx(dev->path.mmio.addr, &idx) == CB_SUCCESS) - return uart_info[idx].acpi_name; + size_t num_ctrlrs; + const struct soc_uart_ctrlr_info *ctrlr = soc_get_uart_ctrlr_info(&num_ctrlrs); + + if (get_uart_idx(dev->path.mmio.addr, ctrlr, num_ctrlrs, &idx) == CB_SUCCESS) + return ctrlr[idx].acpi_name; else return NULL; } -- To view, visit https://review.coreboot.org/c/coreboot/+/68534 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I474e47059eaebcf0b9b77f66ee993f1963ebee77 Gerrit-Change-Number: 68534 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/skyrim: Enable genesyslogic gl9755 for frostflow
by Karthik Ramasubramanian (Code Review) 20 Oct '22

20 Oct '22

Attention is currently required from: Frank Wu, Jason Nien, Kangheui Won, Isaac Lee, Jon Murphy, Angel Pons, Martin Roth. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68483 ) Change subject: mb/google/skyrim: Enable genesyslogic gl9755 for frostflow ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68483 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1db598c68687ed17fd9baa3567ab8fdd3e4fb6a8 Gerrit-Change-Number: 68483 Gerrit-PatchSet: 5 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Chao Gui <chaogui(a)google.com> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Isaac Lee <isaaclee(a)google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Thu, 20 Oct 2022 16:42:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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