coreboot-gerrit October 2022

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: soc/amd: Add AMDFW_CONTAINS_FIRST_BIOS_BLOCK config item
by Karthik Ramasubramanian (Code Review) 20 Oct '22

20 Oct '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Julius Werner, Fred Reitberger, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68229 ) Change subject: soc/amd: Add AMDFW_CONTAINS_FIRST_BIOS_BLOCK config item ...................................................................... Patch Set 6: (1 comment) File src/soc/amd/mendocino/Kconfig: https://review.coreboot.org/c/coreboot/+/68229/comment/d239d429_74bb542d PS2, Line 367: y > I am not finding an equivalent one yet, but I dont have all the historical context. […] Thanks to Raul for pointing out that there is an equivalent Kconfig `RESET_VECTOR_IN_RAM`. This is used by AMD SoCs where PSP loads the bootblock in preinitialized DRAM before releasing x86 out of reset. -- To view, visit https://review.coreboot.org/c/coreboot/+/68229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00cab18233edde597ddf90f83e32731cca741e15 Gerrit-Change-Number: 68229 Gerrit-PatchSet: 6 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 20 Oct 2022 17:44:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/prodrive/atlas: Disable S3
by Maximilian Brune (Code Review) 20 Oct '22

20 Oct '22

Attention is currently required from: Christian Walter, Maximilian Brune, Angel Pons, Lean Sheng Tan. Hello build bot (Jenkins), Christian Walter, Angel Pons, Lean Sheng Tan, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68591 to look at the new patch set (#2). Change subject: mb/prodrive/atlas: Disable S3 ...................................................................... mb/prodrive/atlas: Disable S3 The Atlas board has currenlty the problem that suspending the System causes the System to freeze. Therefore disable S3, until the cause is figured out and fixed. Change-Id: I5b28787df9b01683fcd4a1de8267840a80bb4fe6 Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> --- M src/mainboard/prodrive/atlas/Kconfig 1 file changed, 14 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/68591/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68591 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b28787df9b01683fcd4a1de8267840a80bb4fe6 Gerrit-Change-Number: 68591 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: arch/x86: Don't use .bss from car.ld if not running XIP
by Arthur Heymans (Code Review) 20 Oct '22

20 Oct '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48156 ) Change subject: arch/x86: Don't use .bss from car.ld if not running XIP ...................................................................... arch/x86: Don't use .bss from car.ld if not running XIP Some platform run early stages like romstage and verstage from CAR instead of XIP. This allows to link them like other arch inside the _program region. Change-Id: I6cf51f943dde5f642d75ba4c5d3be520dc56370a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/assembly_entry.S M src/arch/x86/car.ld M src/include/rules.h M src/lib/program.ld 4 files changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/48156/1 diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S index 31670c2..7d7d3fc 100644 --- a/src/arch/x86/assembly_entry.S +++ b/src/arch/x86/assembly_entry.S @@ -36,6 +36,7 @@ mov $_STACK_TOP, %esp /* clear .bss section as it is not shared */ +#if ENV_STAGE_XIP cld xor %eax, %eax movl $(_ebss), %ecx @@ -43,6 +44,7 @@ sub %edi, %ecx shrl $2, %ecx rep stosl +#endif #if ((ENV_SEPARATE_VERSTAGE && CONFIG(VERSTAGE_DEBUG_SPINLOOP)) \ || (ENV_ROMSTAGE && CONFIG(ROMSTAGE_DEBUG_SPINLOOP))) diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index c291efb..38128d1 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -62,6 +62,7 @@ * cbmem console. This is useful for clearing this area on a per-stage * basis when more than one stage uses cache-as-ram. */ +#if ENV_STAGE_HAS_CAR_XIP_BSS . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _bss = .; /* Allow global uninitialized variables for stages without CAR teardown. */ @@ -71,6 +72,7 @@ *(.sbss.*) . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _ebss = .; +#endif #if ENV_ROMSTAGE && CONFIG(ASAN_IN_ROMSTAGE) _shadow_size = (_ebss - _car_region_start) >> 3; diff --git a/src/include/rules.h b/src/include/rules.h index 6ebb37e..f503914 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -261,14 +261,21 @@ #if ENV_X86 /* Indicates memory layout is determined with arch/x86/car.ld. */ #define ENV_CACHE_AS_RAM (ENV_ROMSTAGE_OR_BEFORE && !CONFIG(RESET_VECTOR_IN_RAM)) +/* Indicates if the stage runs XIP. */ +#define ENV_STAGE_XIP (ENV_CACHE_AS_RAM && \ + !((ENV_ROMSTAGE || ENV_SEPARATE_VERSTAGE) && CONFIG(NO_XIP_EARLY_STAGES))) /* No .data sections with execute-in-place from ROM. */ #define ENV_STAGE_HAS_DATA_SECTION !ENV_CACHE_AS_RAM #else /* Both .data and .bss, sometimes SRAM not DRAM. */ #define ENV_STAGE_HAS_DATA_SECTION 1 #define ENV_CACHE_AS_RAM 0 +#define ENV_STAGE_XIP 0 #endif +/* Indicates if the stages uses the _bss region defined in arch/x86/car.ld */ +#define ENV_STAGE_HAS_CAR_XIP_BSS ENV_STAGE_XIP + /* Currently rmodules, ramstage and smm have heap. */ #define ENV_STAGE_HAS_HEAP_SECTION (ENV_RMODULE || ENV_RAMSTAGE || ENV_SMM) diff --git a/src/lib/program.ld b/src/lib/program.ld index 3b6aa2e..ff3c672 100644 --- a/src/lib/program.ld +++ b/src/lib/program.ld @@ -103,7 +103,7 @@ } #endif -#if !ENV_CACHE_AS_RAM +#if !ENV_STAGE_HAS_CAR_XIP_BSS .bss . : { . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _bss = .; -- To view, visit https://review.coreboot.org/c/coreboot/+/48156 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cf51f943dde5f642d75ba4c5d3be520dc56370a Gerrit-Change-Number: 48156 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: drivers/intel/fsp2_0/memory_init.c: clean code
by Maximilian Brune (Code Review) 20 Oct '22

20 Oct '22

Attention is currently required from: Maximilian Brune, Andrey Petrov. Hello build bot (Jenkins), Andrey Petrov, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68592 to look at the new patch set (#2). Change subject: drivers/intel/fsp2_0/memory_init.c: clean code ...................................................................... drivers/intel/fsp2_0/memory_init.c: clean code Change-Id: I4d57c45ede520160ef615725c023b7e92289a995 Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> --- M src/drivers/intel/fsp2_0/memory_init.c 1 file changed, 13 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/68592/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68592 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d57c45ede520160ef615725c023b7e92289a995 Gerrit-Change-Number: 68592 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/amd/morgana: Add TODOs for common code to Kconfig
by Felix Held (Code Review) 20 Oct '22

20 Oct '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68555 ) Change subject: soc/amd/morgana: Add TODOs for common code to Kconfig ...................................................................... soc/amd/morgana: Add TODOs for common code to Kconfig This allows us to see which of the common code blocks have been verified and which have not. Signed-off-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Change-Id: Icb9eba5838013de75c408c28a4a7d3afacdf0674 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68555 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/morgana/Kconfig 1 file changed, 56 insertions(+), 40 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/morgana/Kconfig b/src/soc/amd/morgana/Kconfig index f150d51..a1261c9 100644 --- a/src/soc/amd/morgana/Kconfig +++ b/src/soc/amd/morgana/Kconfig @@ -39,46 +39,46 @@ select RESET_VECTOR_IN_RAM select RTC select SOC_AMD_COMMON - select SOC_AMD_COMMON_BLOCK_ACP_GEN2 - select SOC_AMD_COMMON_BLOCK_ACPI - select SOC_AMD_COMMON_BLOCK_ACPIMMIO - select SOC_AMD_COMMON_BLOCK_ACPI_ALIB - select SOC_AMD_COMMON_BLOCK_ACPI_CPPC - select SOC_AMD_COMMON_BLOCK_ACPI_GPIO - select SOC_AMD_COMMON_BLOCK_ACPI_IVRS - select SOC_AMD_COMMON_BLOCK_AOAC - select SOC_AMD_COMMON_BLOCK_APOB - select SOC_AMD_COMMON_BLOCK_APOB_HASH - select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS - select SOC_AMD_COMMON_BLOCK_DATA_FABRIC - select SOC_AMD_COMMON_BLOCK_EMMC - select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES - select SOC_AMD_COMMON_BLOCK_GRAPHICS - select SOC_AMD_COMMON_BLOCK_HAS_ESPI - select SOC_AMD_COMMON_BLOCK_HAS_ESPI_ALERT_ENABLE - select SOC_AMD_COMMON_BLOCK_I2C - select SOC_AMD_COMMON_BLOCK_I23C_PAD_CTRL - select SOC_AMD_COMMON_BLOCK_IOMMU - select SOC_AMD_COMMON_BLOCK_LPC - select SOC_AMD_COMMON_BLOCK_MCAX - select SOC_AMD_COMMON_BLOCK_NONCAR - select SOC_AMD_COMMON_BLOCK_PCI - select SOC_AMD_COMMON_BLOCK_PCI_MMCONF - select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER - select SOC_AMD_COMMON_BLOCK_PM - select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE - select SOC_AMD_COMMON_BLOCK_PSP_GEN2 - select SOC_AMD_COMMON_BLOCK_SMBUS - select SOC_AMD_COMMON_BLOCK_SMI - select SOC_AMD_COMMON_BLOCK_SMM - select SOC_AMD_COMMON_BLOCK_SMU - select SOC_AMD_COMMON_BLOCK_SPI - select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H - select SOC_AMD_COMMON_BLOCK_UART - select SOC_AMD_COMMON_BLOCK_UCODE - select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB - select SOC_AMD_COMMON_FSP_DMI_TABLES - select SOC_AMD_COMMON_FSP_PCI + select SOC_AMD_COMMON_BLOCK_ACP_GEN2 # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_ACPI # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_ACPIMMIO # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_ACPI_ALIB # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_ACPI_CPPC # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_ACPI_GPIO # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_ACPI_IVRS # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_AOAC # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_APOB # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_APOB_HASH # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_DATA_FABRIC # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_EMMC # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_GRAPHICS # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_HAS_ESPI # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_HAS_ESPI_ALERT_ENABLE # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_I2C # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_I23C_PAD_CTRL # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_IOMMU # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_LPC # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_MCAX # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_NONCAR # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_PCI # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_PCI_MMCONF # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_PM # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_PSP_GEN2 # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_SMBUS # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_SMI # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_SMM # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_SMU # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_SPI # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_UART # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_UCODE # TODO: Check if this is still correct + select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB # TODO: Check if this is still correct + select SOC_AMD_COMMON_FSP_DMI_TABLES # TODO: Check if this is still correct + select SOC_AMD_COMMON_FSP_PCI # TODO: Check if this is still correct select SSE2 select UDK_2017_BINDING select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM -- To view, visit https://review.coreboot.org/c/coreboot/+/68555 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb9eba5838013de75c408c28a4a7d3afacdf0674 Gerrit-Change-Number: 68555 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/amd/morgana: Add TODOs for common code to Kconfig
by Felix Held (Code Review) 20 Oct '22

20 Oct '22

Attention is currently required from: Martin L Roth, Martin Roth. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68555 ) Change subject: soc/amd/morgana: Add TODOs for common code to Kconfig ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68555 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb9eba5838013de75c408c28a4a7d3afacdf0674 Gerrit-Change-Number: 68555 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Thu, 20 Oct 2022 17:31:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: nb/intel/i945: Clean up includes
by Martin Roth (Code Review) 20 Oct '22

20 Oct '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68211 ) Change subject: nb/intel/i945: Clean up includes ...................................................................... nb/intel/i945: Clean up includes Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Change-Id: I0e5f102d75647c9c184cb7422af30c9196503882 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68211 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/i945/errata.c M src/northbridge/intel/i945/i945.h M src/northbridge/intel/i945/romstage.c 3 files changed, 20 insertions(+), 11 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/northbridge/intel/i945/errata.c b/src/northbridge/intel/i945/errata.c index 3057ae9..c4219d9 100644 --- a/src/northbridge/intel/i945/errata.c +++ b/src/northbridge/intel/i945/errata.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <stdint.h> + #include "i945.h" #include "raminit.h" diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index d8993ac..3470a77 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -3,10 +3,11 @@ #ifndef NORTHBRIDGE_INTEL_I945_H #define NORTHBRIDGE_INTEL_I945_H -#define DEFAULT_X60BAR 0xfed13000 - +#include <northbridge/intel/common/fixed_bars.h> #include <southbridge/intel/i82801gx/i82801gx.h> +#define DEFAULT_X60BAR 0xfed13000 + /* Everything below this line is ignored in the DSDT */ #ifndef __ACPI__ @@ -86,12 +87,6 @@ #define BSM 0x5c #define GCFC 0xf0 /* Graphics Clock Frequency & Gating Control */ -/* - * MCHBAR - */ - -#include <northbridge/intel/common/fixed_bars.h> - /* Chipset Control Registers */ #define FSBPMC3 0x40 /* 32bit */ #define FSBPMC4 0x44 /* 32bit */ diff --git a/src/northbridge/intel/i945/romstage.c b/src/northbridge/intel/i945/romstage.c index 0a61780..61b9bcf 100644 --- a/src/northbridge/intel/i945/romstage.c +++ b/src/northbridge/intel/i945/romstage.c @@ -1,12 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdint.h> -#include <cf9_reset.h> #include <arch/romstage.h> +#include <cf9_reset.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> -#include <southbridge/intel/i82801gx/i82801gx.h> #include <southbridge/intel/common/pmclib.h> +#include <southbridge/intel/i82801gx/i82801gx.h> +#include <stdint.h> __weak void mainboard_lpc_decode(void) { -- To view, visit https://review.coreboot.org/c/coreboot/+/68211 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e5f102d75647c9c184cb7422af30c9196503882 Gerrit-Change-Number: 68211 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: intel/i945: Use 'bool' for dual_channel and interleaved
by Martin Roth (Code Review) 20 Oct '22

20 Oct '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67925 ) Change subject: intel/i945: Use 'bool' for dual_channel and interleaved ...................................................................... intel/i945: Use 'bool' for dual_channel and interleaved Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Change-Id: I055847c9b08795683fe2e1dfd7fcde49901fc973 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67925 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/i945/raminit.c M src/northbridge/intel/i945/raminit.h 2 files changed, 26 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 2ab4d10..c9b0837 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -314,10 +314,10 @@ printk(BIOS_DEBUG, "This mainboard supports "); if (sdram_capabilities_dual_channel()) { - sysinfo->dual_channel = 1; + sysinfo->dual_channel = true; printk(BIOS_DEBUG, "Dual Channel Operation.\n"); } else { - sysinfo->dual_channel = 0; + sysinfo->dual_channel = false; printk(BIOS_DEBUG, "only Single Channel Operation.\n"); } @@ -765,7 +765,7 @@ DQ2330, NC, CTL3215, NC, CLK2030, CLK2030, DQ2030, CMD3210 }; -static const u32 *slew_group_lookup(int dual_channel, int index) +static const u32 *slew_group_lookup(bool dual_channel, int index) { const u8 *slew_group; /* Dual Channel needs different tables. */ @@ -902,7 +902,8 @@ static void sdram_rcomp_buffer_strength_and_slew(struct sys_info *sysinfo) { const u8 *strength_multiplier; - int idx, dual_channel; + int idx; + bool dual_channel; /* Set Strength Multipliers */ @@ -910,12 +911,12 @@ if (sdram_capabilities_dual_channel()) { printk(BIOS_DEBUG, "Programming Dual Channel RCOMP\n"); strength_multiplier = dual_channel_strength_multiplier; - dual_channel = 1; + dual_channel = true; idx = 5 * sysinfo->dimm[0] + sysinfo->dimm[2]; } else { printk(BIOS_DEBUG, "Programming Single Channel RCOMP\n"); strength_multiplier = single_channel_strength_multiplier; - dual_channel = 0; + dual_channel = false; idx = 5 * sysinfo->dimm[0] + sysinfo->dimm[1]; } @@ -1536,9 +1537,9 @@ (sysinfo->banksize[4] + sysinfo->banksize[5] + sysinfo->banksize[6] + sysinfo->banksize[7]))) { /* Both channels equipped with DIMMs of the same size */ - sysinfo->interleaved = 1; + sysinfo->interleaved = true; } else { - sysinfo->interleaved = 0; + sysinfo->interleaved = false; } reg32 = mchbar_read32(DCC); diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h index 513984f..d69110e 100644 --- a/src/northbridge/intel/i945/raminit.h +++ b/src/northbridge/intel/i945/raminit.h @@ -3,6 +3,8 @@ #ifndef RAMINIT_H #define RAMINIT_H +#include <types.h> + #define DIMM_SOCKETS 2 #define DIMM_TCO_BASE 0x30 @@ -24,8 +26,8 @@ u8 cas; /* 3, 4 or 5 */ u8 refresh; /* 0 = 15.6us, 1 = 7.8us */ - u8 dual_channel; /* 0 or 1 */ - u8 interleaved; + bool dual_channel; + bool interleaved; u8 mvco4x; /* 0 (8x) or 1 (4x) */ u8 clkcfg_bit7; -- To view, visit https://review.coreboot.org/c/coreboot/+/67925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I055847c9b08795683fe2e1dfd7fcde49901fc973 Gerrit-Change-Number: 67925 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: drivers/tpm: Move TPM init to end of device init phase
by Felix Held (Code Review) 20 Oct '22

20 Oct '22

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68550 ) Change subject: drivers/tpm: Move TPM init to end of device init phase ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: if possible i'd like if this was moved over to use device operations instead of boot state hooks, since i'd assume that this would take the dependencies into account -- To view, visit https://review.coreboot.org/c/coreboot/+/68550 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic47e465db1c06d8b79a1f0a06906843149b6dacd Gerrit-Change-Number: 68550 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Alexandru Stan <amstan(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 20 Oct 2022 17:27:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: nb/intel/i945/rcven.c: Use read32p()
by Martin Roth (Code Review) 20 Oct '22

20 Oct '22

Attention is currently required from: Elyes Haouas. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68087 ) Change subject: nb/intel/i945/rcven.c: Use read32p() ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1935308cc50abd651b52d6290d66180905c6a521 Gerrit-Change-Number: 68087 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 20 Oct 2022 17:27:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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