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Change subject: soc/amd/mendocino: Reserve more space for metadata
......................................................................
Patch Set 13:
(1 comment)
File src/soc/amd/mendocino/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/66944/comment/67f1fade_0a204ee5
PS8, Line 77: # 0x40 accounts for the cbfs_file struct + filename + metadata structs, aligned to 64 bytes
: # Building the cbfs image will fail if the offset isn't large enough
> Kept 0x80 for all to accommodate the metadata hash attribute. […]
Done
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Change subject: soc/amd: Add amdfw.rom in coreboot.pre
......................................................................
Patch Set 14:
(1 comment)
File src/soc/amd/common/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/66943/comment/b8920167_fea94c3f
PS8, Line 23: $(call int-add, \
: $(call int-subtract, 0xffffffff \
: $(call int-shift-left, \
: 0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000 1)
> Does this help - https://review.coreboot. […]
I take your comment on CB:68584 as we are going in the right direction. Hence marking this as resolved and address all your comments in that one.
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Change subject: util/amdfwtool/amdfwread: Update relative_offset function
......................................................................
Patch Set 15:
(1 comment)
File util/amdfwtool/amdfwread.c:
https://review.coreboot.org/c/coreboot/+/66572/comment/9647b7d9_a8af2ee6
PS13, Line 38: /* Intentional fall-through */
> Ah, well glad it caught it. […]
Done
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#10).
Change subject: soc/amd/mendocino: Update build rules for PSP BIOS image
......................................................................
soc/amd/mendocino: Update build rules for PSP BIOS image
Do not compress PSP BIOS image when CBFS verification is enabled.
Otherwise when a file is added to CBFS, cbfstool is not able to find the
metadata hash anchor magic in the compressed PSP BIOS image.
BUG=b:227809919
TEST=Build and boot to OS in Skyrim with CBFS verification enabled for
both x86 and PSP verstage.
Change-Id: Iaed888b81d14ede77132ff48abcfbeb138c01ce4
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
---
M src/soc/amd/mendocino/Makefile.inc
1 file changed, 24 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/68136/10
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I'd like you to reexamine a change. Please visit
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Change subject: soc/amd: Add amdfw.rom in coreboot.pre
......................................................................
soc/amd: Add amdfw.rom in coreboot.pre
This change ensures that amdfw.rom binary containing metadata hash
anchor is added before any file is added to CBFS. This will allow to
verify all the CBFS files that are not excluded from verification.
BUG=b:227809919
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x86 and PSP verstages.
Change-Id: Id4d1a2d8b145cbbbf2da27aa73b296c9c8a65209
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
---
M src/soc/amd/cezanne/Makefile.inc
M src/soc/amd/common/Makefile.inc
M src/soc/amd/mendocino/Makefile.inc
M src/soc/amd/morgana/Makefile.inc
M src/soc/amd/picasso/Makefile.inc
5 files changed, 30 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/66943/14
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Change subject: util/amdfwtool/amdfwread: Update relative_offset function
......................................................................
util/amdfwtool/amdfwread: Update relative_offset function
* AMD_ADDR_PHYSICAL refers to physical address in the memory map
* AMD_ADDR_REL_BIOS is relative to the start of the BIOS image
* AMD_ADDR_REL_TAB is relative to the start of concerned PSP or BIOS
tables
Update the relative_offset implementation accordingly. Though
AMD_ADDR_REL_SLOT is defined it is not used. Removing that to simplify
the relative_offset implementation so that it can be used for both PSP
and BIOS firmware tables. Hence update the relative_offset function
signature as well.
BUG=None
TEST=Build and use amdfwread to read the Soft-fuse bits from Guybrush
BIOS image. Observed no changes before and after the changes.
Change-Id: I74603dd08eda87393c14b746c4435eaf2bb34126
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---
M util/amdfwtool/amdfwread.c
1 file changed, 53 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/66572/15
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Change subject: soc/intel/alderlake: Hook up DisableDynamicTccoldHandshake to dev tree
......................................................................
Patch Set 5: Code-Review+2
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Change subject: vendorcode/intel/fsp: Add Raptor Lake FSP headers for FSP RPL.3361.07
......................................................................
Patch Set 2: Code-Review-1
(1 comment)
Patchset:
PS2:
Blocking change from merging until FSP uprev CLs are ready to merge.
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Change subject: mb/google/brya/var/skolas: disable Tccold Handshake
......................................................................
Patch Set 3: Code-Review+1
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