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Change subject: mb/google/skyrim: Enable CBFS Verification
......................................................................
Patch Set 14:
(1 comment)
File src/soc/amd/mendocino/cbfs_verify.c:
https://review.coreboot.org/c/coreboot/+/66948/comment/5d26f041_5c4e9787
PS3, Line 12: uint32_t mh_offset = FMAP_SECTION_COREBOOT_START - FMAP_SECTION_FLASH_START
: + CONFIG_METADATA_HASH_CBFS_OFFSET;
:
: if (!CONFIG(CBFS_VERIFICATION))
: return 0;
:
: boot_device_init();
: boot_dev = boot_device_ro();
: if (!boot_dev || rdev_readat(boot_dev, &mdata_hash, mh_offset,
: sizeof(mdata_hash)) != sizeof(mdata_hash)) {
: printk(BIOS_ERR, "Error reading metadata hash FMAP section\n");
: return -1;
: }
: metadata_hash_import_anchor(&mdata_hash);
: return 0;
> Can delete this once it's part of the vboot infrastructure.
No need for it anymore.
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Change subject: soc/amd/mendocino: Add GSVCD range
......................................................................
Patch Set 13:
(1 comment)
File src/soc/amd/common/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/66945/comment/33b850e6_9fd6cf77
PS12, Line 35: awk '/$(1)/ {print $$4}'
> You could do the offset and size in one command can't you? […]
Done
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Matt DeVillier, Julius Werner, Fred Reitberger, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/66945
to look at the new patch set (#13).
Change subject: soc/amd/mendocino: Add GSVCD range
......................................................................
soc/amd/mendocino: Add GSVCD range
Add region/range of SPI ROM to be verified by Google Security Chip
(GSC).
BUG=b:227809919
TEST=Build and boot to OS in Skyrim with CBFS verification enabled.
Change-Id: If8a766d9a7ef26f94e3ab002a9384ba9d444dd1f
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
---
M src/soc/amd/common/Makefile.inc
M src/soc/amd/mendocino/Makefile.inc
2 files changed, 41 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/66945/13
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Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68525 )
Change subject: soc/intel: Add node_num to dimm_info struct + adjust dimm_info_fill
......................................................................
Patch Set 4:
(1 comment)
File src/include/memory_info.h:
https://review.coreboot.org/c/coreboot/+/68525/comment/0bcf4519_e70ea6b8
PS4, Line 96: * Node-ID / Memory-Controller-ID
> Alder Lake (Client) processors have 2 memory controllers in a single socket.
Yes, similar like on the server side, the hierarchy is socket/controller/channel/DIMM.
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Change subject: soc/intel/xeon_sp: Add functions to store/restore uart state in smm
......................................................................
Patch Set 4: Code-Review+1
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Change subject: configs: Build-test ACPI EINJ with OCP Delta Lake
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68681/comment/6c47d314_f0be5920
PS1, Line 9: Add a config file to build-test the `ACPI_EINJ` Kconfig option.
Should we just update configs/builder/config.ocp.deltalake?
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