coreboot-gerrit October 2022

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[M] Change in coreboot[master]: soc/amd/morgana/mca: Update for morgana
by Fred Reitberger (Code Review) 21 Oct '22

21 Oct '22

Fred Reitberger has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68683 ) Change subject: soc/amd/morgana/mca: Update for morgana ...................................................................... soc/amd/morgana/mca: Update for morgana Update the MCA bank names for morgana per PPR #57396, rev 1.52 Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Change-Id: If0082bd5362bdead3f9dc693d1e338e8cda224f0 --- M src/soc/amd/morgana/mca.c 1 file changed, 65 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/68683/1 diff --git a/src/soc/amd/morgana/mca.c b/src/soc/amd/morgana/mca.c index c104a33..63b040b 100644 --- a/src/soc/amd/morgana/mca.c +++ b/src/soc/amd/morgana/mca.c @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* TODO: Update for Morgana */ - #include <amdblocks/mca.h> #include <cpu/x86/msr.h> #include <types.h> @@ -18,12 +16,59 @@ [8] = "L3 cache unit", [9] = "L3 cache unit", [10] = "L3 cache unit", - [11] = "UMC", - [12] = "UMC", - [13] = "CS", - [14] = "CS", - [15] = "NBIO", - [16] = "PIE", + [11] = "L3 cache unit", + [12] = "L3 cache unit", + [13] = "L3 cache unit", + [14] = "L3 cache unit", + [15] = "UMC", + [16] = "UMC", + [17] = "UMC", + [18] = "UMC", + [19] = "CS", + [20] = "CS", + [21] = "CS", + [22] = "CS", + [23] = "", + [24] = "", + [25] = "NBIO", + [26] = "", + [27] = "", + [28] = "PIE", + [29] = "", + [30] = "", + [31] = "", + [32] = "", + [33] = "", + [34] = "", + [35] = "", + [36] = "", + [37] = "", + [38] = "", + [39] = "", + [40] = "", + [41] = "", + [42] = "", + [43] = "", + [44] = "", + [45] = "", + [46] = "", + [47] = "", + [48] = "", + [49] = "", + [50] = "", + [51] = "", + [52] = "", + [53] = "", + [54] = "", + [55] = "", + [56] = "", + [57] = "", + [58] = "", + [59] = "", + [60] = "", + [61] = "", + [62] = "", + [63] = "", }; bool mca_has_expected_bank_count(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/68683 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0082bd5362bdead3f9dc693d1e338e8cda224f0 Gerrit-Change-Number: 68683 Gerrit-PatchSet: 1 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd/*/i2c.h: Make definition more accurate
by Fred Reitberger (Code Review) 21 Oct '22

21 Oct '22

Fred Reitberger has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68682 ) Change subject: soc/amd/*/i2c.h: Make definition more accurate ...................................................................... soc/amd/*/i2c.h: Make definition more accurate Make GPIO_I2C_MASK macro more accurate by using the GPIO_I2Cx_SCL definitions instead of BIT(x). Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Change-Id: I13fc376552068a64768fe1cf9f1c09cca1768aed --- M src/soc/amd/cezanne/include/soc/i2c.h M src/soc/amd/mendocino/include/soc/i2c.h M src/soc/amd/picasso/include/soc/i2c.h M src/soc/amd/stoneyridge/include/soc/i2c.h 4 files changed, 20 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/68682/1 diff --git a/src/soc/amd/cezanne/include/soc/i2c.h b/src/soc/amd/cezanne/include/soc/i2c.h index c0e3e80..fa7a5e4 100644 --- a/src/soc/amd/cezanne/include/soc/i2c.h +++ b/src/soc/amd/cezanne/include/soc/i2c.h @@ -10,7 +10,8 @@ #define GPIO_I2C1_SCL BIT(1) #define GPIO_I2C2_SCL BIT(2) #define GPIO_I2C3_SCL BIT(3) -#define GPIO_I2C_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) +#define GPIO_I2C_MASK (GPIO_I2C0_SCL | GPIO_I2C1_SCL | \ + GPIO_I2C2_SCL | GPIO_I2C3_SCL) #define I2C0_SCL_PIN GPIO_145 diff --git a/src/soc/amd/mendocino/include/soc/i2c.h b/src/soc/amd/mendocino/include/soc/i2c.h index 157ac86..c691267 100644 --- a/src/soc/amd/mendocino/include/soc/i2c.h +++ b/src/soc/amd/mendocino/include/soc/i2c.h @@ -10,7 +10,8 @@ #define GPIO_I2C1_SCL BIT(1) #define GPIO_I2C2_SCL BIT(2) #define GPIO_I2C3_SCL BIT(3) -#define GPIO_I2C_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) +#define GPIO_I2C_MASK (GPIO_I2C0_SCL | GPIO_I2C1_SCL | \ + GPIO_I2C2_SCL | GPIO_I2C3_SCL) #define I2C0_SCL_PIN GPIO_145 diff --git a/src/soc/amd/picasso/include/soc/i2c.h b/src/soc/amd/picasso/include/soc/i2c.h index 7056272..6a4d1ff 100644 --- a/src/soc/amd/picasso/include/soc/i2c.h +++ b/src/soc/amd/picasso/include/soc/i2c.h @@ -8,7 +8,7 @@ #define GPIO_I2C2_SCL BIT(2) #define GPIO_I2C3_SCL BIT(3) -#define GPIO_I2C_MASK (BIT(2) | BIT(3)) +#define GPIO_I2C_MASK (GPIO_I2C2_SCL | GPIO_I2C3_SCL) #define I2C2_SCL_PIN GPIO_113 #define I2C3_SCL_PIN GPIO_19 diff --git a/src/soc/amd/stoneyridge/include/soc/i2c.h b/src/soc/amd/stoneyridge/include/soc/i2c.h index 505802e..0ffff37 100644 --- a/src/soc/amd/stoneyridge/include/soc/i2c.h +++ b/src/soc/amd/stoneyridge/include/soc/i2c.h @@ -10,7 +10,8 @@ #define GPIO_I2C1_SCL BIT(1) #define GPIO_I2C2_SCL BIT(2) #define GPIO_I2C3_SCL BIT(3) -#define GPIO_I2C_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) +#define GPIO_I2C_MASK (GPIO_I2C0_SCL | GPIO_I2C1_SCL | \ + GPIO_I2C2_SCL | GPIO_I2C3_SCL) #define I2C0_SCL_PIN GPIO_145 #define I2C1_SCL_PIN GPIO_147 -- To view, visit https://review.coreboot.org/c/coreboot/+/68682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13fc376552068a64768fe1cf9f1c09cca1768aed Gerrit-Change-Number: 68682 Gerrit-PatchSet: 1 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[master]: mb/gigabyte/ga-h61m-series: Add GA-H61M-DS2
by Angel Pons (Code Review) 21 Oct '22

21 Oct '22

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61541 ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/gigabyte/ga-h61m-series: Add GA-H61M-DS2 ...................................................................... mb/gigabyte/ga-h61m-series: Add GA-H61M-DS2 Built from a mixture of autoport output, other variants, schematics and expert guesswork. I don't have this board, but the code has been tested by someone else and boots successfully (first try) with TianoCore. It's reasonable to assume most things work, as this board is very similar to the already-supported variants. Change-Id: I3d8df483e5573f77782b7d18b1410b391bfe387d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61541 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/gigabyte/ga-h61m-series/Kconfig M src/mainboard/gigabyte/ga-h61m-series/Kconfig.name A src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2/gpio.c A src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2/hda_verb.c A src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2/overridetree.cb 5 files changed, 307 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Arthur Heymans: Looks good to me, approved diff --git a/src/mainboard/gigabyte/ga-h61m-series/Kconfig b/src/mainboard/gigabyte/ga-h61m-series/Kconfig index cec2c61..8f4366b 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/Kconfig +++ b/src/mainboard/gigabyte/ga-h61m-series/Kconfig @@ -1,9 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only -if BOARD_GIGABYTE_GA_H61M_S2PV || BOARD_GIGABYTE_GA_H61M_DS2V || BOARD_GIGABYTE_GA_H61MA_D3V - -config BOARD_SPECIFIC_OPTIONS - def_bool y +config BOARD_GIGABYTE_GA_H61M_SERIES + def_bool n select BOARD_ROMSIZE_KB_4096 select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES @@ -18,6 +16,8 @@ select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT +if BOARD_GIGABYTE_GA_H61M_SERIES + config MAINBOARD_DIR default "gigabyte/ga-h61m-series" @@ -25,11 +25,13 @@ default "ga-h61m-s2pv" if BOARD_GIGABYTE_GA_H61M_S2PV default "ga-h61m-ds2v" if BOARD_GIGABYTE_GA_H61M_DS2V default "ga-h61ma-d3v" if BOARD_GIGABYTE_GA_H61MA_D3V + default "ga-h61m-ds2" if BOARD_GIGABYTE_GA_H61M_DS2 config MAINBOARD_PART_NUMBER default "GA-H61M-S2PV" if BOARD_GIGABYTE_GA_H61M_S2PV default "GA-H61M-DS2V" if BOARD_GIGABYTE_GA_H61M_DS2V default "GA-H61MA-D3V" if BOARD_GIGABYTE_GA_H61MA_D3V + default "GA-H61M-DS2" if BOARD_GIGABYTE_GA_H61M_DS2 config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" @@ -42,4 +44,4 @@ int default 2 -endif # BOARD_GIGABYTE_GA_H61M* +endif # BOARD_GIGABYTE_GA_H61M_SERIES diff --git a/src/mainboard/gigabyte/ga-h61m-series/Kconfig.name b/src/mainboard/gigabyte/ga-h61m-series/Kconfig.name index 15d107d..f584a28 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/Kconfig.name +++ b/src/mainboard/gigabyte/ga-h61m-series/Kconfig.name @@ -1,10 +1,17 @@ config BOARD_GIGABYTE_GA_H61M_S2PV bool "GA-H61M-S2PV" + select BOARD_GIGABYTE_GA_H61M_SERIES + +config BOARD_GIGABYTE_GA_H61M_DS2 + bool "GA-H61M-DS2" + select BOARD_GIGABYTE_GA_H61M_SERIES config BOARD_GIGABYTE_GA_H61M_DS2V bool "GA-H61M-DS2V" + select BOARD_GIGABYTE_GA_H61M_SERIES select NO_UART_ON_SUPERIO config BOARD_GIGABYTE_GA_H61MA_D3V bool "GA-H61MA-D3V" + select BOARD_GIGABYTE_GA_H61M_SERIES select NO_UART_ON_SUPERIO diff --git a/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2/gpio.c b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2/gpio.c new file mode 100644 index 0000000..8c04b38 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2/gpio.c @@ -0,0 +1,189 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio11 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2/hda_verb.c b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2/hda_verb.c new file mode 100644 index 0000000..659d1b6 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2/hda_verb.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0887, /* Codec Vendor / Device ID: Realtek ALC887 */ + 0x1458a002, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(2, 0x1458a002), + AZALIA_PIN_CFG(2, 0x11, 0x411110f0), + AZALIA_PIN_CFG(2, 0x12, 0x411111f0), + AZALIA_PIN_CFG(2, 0x14, 0x01014410), + AZALIA_PIN_CFG(2, 0x15, 0x411111f0), + AZALIA_PIN_CFG(2, 0x16, 0x411111f0), + AZALIA_PIN_CFG(2, 0x17, 0x411111f0), + AZALIA_PIN_CFG(2, 0x18, 0x01a19c20), + AZALIA_PIN_CFG(2, 0x19, 0x02a19c30), + AZALIA_PIN_CFG(2, 0x1a, 0x0181342f), + AZALIA_PIN_CFG(2, 0x1b, 0x02214c1f), + AZALIA_PIN_CFG(2, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(2, 0x1d, 0x4004c601), + AZALIA_PIN_CFG(2, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(2, 0x1f, 0x411111f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2/overridetree.cb b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2/overridetree.cb new file mode 100644 index 0000000..3de7954 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2/overridetree.cb @@ -0,0 +1,56 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/intel/sandybridge + device domain 0 on + + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + + register "pcie_port_coalesce" = "true" + + device pci 1c.0 off end # RP #1 + device pci 1c.1 on end # RP #2: PCIe x1 Port (PCIEX1_1) + device pci 1c.2 off end # RP #3: + device pci 1c.3 off end # RP #4: + device pci 1c.4 on end # RP #5: Realtek RTL8111F GbE NIC + device pci 1c.5 on end # RP #6: PCIe x1 Port (PCIEX1_2) + + device pci 1f.0 on # LPC bridge + chip superio/ite/it8728f + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # COM1 + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.2 off end # COM2 + device pnp 2e.3 off end # Parallel port + device pnp 2e.4 on # Environment Controller + io 0x60 = 0x0a30 + io 0x62 = 0x0a20 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + end + device pnp 2e.6 on end # Mouse + device pnp 2e.7 on # GPIO + irq 0x25 = 0x40 + irq 0x26 = 0xf7 + irq 0x27 = 0x10 + irq 0x2c = 0x80 + io 0x60 = 0x0000 + io 0x62 = 0x0a00 + io 0x64 = 0x0000 + irq 0x70 = 0x00 + irq 0x73 = 0x00 + irq 0xc1 = 0x37 + irq 0xcb = 0x00 + irq 0xf0 = 0x10 + irq 0xf1 = 0x42 + irq 0xf6 = 0x1c + end + device pnp 2e.a off end # CIR + end + end + end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/61541 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d8df483e5573f77782b7d18b1410b391bfe387d Gerrit-Change-Number: 61541 Gerrit-PatchSet: 5 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/alderlake: [TEST] Configure EPP at exit stage BS_PAYLOAD_BOOT
by Sridhar Siricilla (Code Review) 21 Oct '22

21 Oct '22

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68670 ) Change subject: soc/intel/alderlake: [TEST] Configure EPP at exit stage BS_PAYLOAD_BOOT ...................................................................... soc/intel/alderlake: [TEST] Configure EPP at exit stage BS_PAYLOAD_BOOT The patch configures the EPP (Energy Performance Preference) at end exit stage of BS_PAYLOAD_BOOT instead configuring as part of CPU feature programming. Existing code can't configure the EPP value beyond the 0x7F, hence configuration is moved at end. Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I2db806ed651789d58dcb01688a11a569768c3122 --- M src/soc/intel/alderlake/cpu.c 1 file changed, 40 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/68670/1 diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index e339d6d..5dfe151 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -7,6 +7,7 @@ */ #include <console/console.h> +#include <bootstate.h> #include <device/pci.h> #include <device/pci_ids.h> #include <cpu/x86/mp.h> @@ -133,11 +134,6 @@ * Lake or Raptor Lake CPUs, as this results in higher uncore power. */ set_energy_perf_bias(7); - const config_t *conf = config_of_soc(); - /* Set energy-performance preference */ - if (conf->enable_energy_perf_pref) - if (check_energy_perf_cap()) - set_energy_perf_pref(conf->energy_perf_pref_value); /* Enable Turbo */ enable_turbo(); @@ -299,3 +295,26 @@ return 0; } } + +static void set_core_epp(void *epp) +{ + set_energy_perf_pref(*(uint8_t *)epp); +} + +static void run_set_core_epp(void *unused) +{ + const config_t *conf = config_of_soc(); + + /* Set energy-performance preference */ + if (conf->enable_energy_perf_pref && check_energy_perf_cap()) { + + uint8_t energy_perf_pref_value = conf->energy_perf_pref_value; + + if (mp_run_on_all_cpus(set_core_epp, &energy_perf_pref_value) != CB_SUCCESS) { + printk(BIOS_ERR, "cpu: Failed to set core EPP\n"); + return; + } + } +} + +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_EXIT, run_set_core_epp, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/68670 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2db806ed651789d58dcb01688a11a569768c3122 Gerrit-Change-Number: 68670 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/brya/var/skolas: disable Tccold Handshake
by Angel Pons (Code Review) 21 Oct '22

21 Oct '22

Attention is currently required from: Bora Guvendik, Subrata Banik, Selma Bensaid, Tim Wawrzynczak, Kane Chen. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68636 ) Change subject: mb/google/brya/var/skolas: disable Tccold Handshake ...................................................................... Patch Set 3: (2 comments) File src/mainboard/google/brya/variants/skolas/overridetree.cb: https://review.coreboot.org/c/coreboot/+/68636/comment/793302a5_89b29c3e PS3, Line 51: 1 nit: true File src/mainboard/google/brya/variants/skolas4es/overridetree.cb: https://review.coreboot.org/c/coreboot/+/68636/comment/c4430002_53fcf4f1 PS3, Line 47: 1 nit: true -- To view, visit https://review.coreboot.org/c/coreboot/+/68636 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic184a61c27abd729667cd181d8f9954f58b67856 Gerrit-Change-Number: 68636 Gerrit-PatchSet: 3 Gerrit-Owner: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Comment-Date: Fri, 21 Oct 2022 18:50:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: configs: Build-test ACPI EINJ with OCP Delta Lake
by Angel Pons (Code Review) 21 Oct '22

21 Oct '22

Attention is currently required from: Jonathan Zhang, Elyes Haouas. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68681 ) Change subject: configs: Build-test ACPI EINJ with OCP Delta Lake ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Hmmm, just realized that the Kconfig option does nothing... -- To view, visit https://review.coreboot.org/c/coreboot/+/68681 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72be1c7e9f0c34c14c48cc7db69cf23d04a36366 Gerrit-Change-Number: 68681 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 21 Oct 2022 18:47:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: configs: Build-test ACPI EINJ with OCP Delta Lake
by Angel Pons (Code Review) 21 Oct '22

21 Oct '22

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68681 ) Change subject: configs: Build-test ACPI EINJ with OCP Delta Lake ...................................................................... configs: Build-test ACPI EINJ with OCP Delta Lake Add a config file to build-test the `ACPI_EINJ` Kconfig option. Change-Id: I72be1c7e9f0c34c14c48cc7db69cf23d04a36366 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A configs/config.ocp_deltalake_acpi_einj 1 file changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/68681/1 diff --git a/configs/config.ocp_deltalake_acpi_einj b/configs/config.ocp_deltalake_acpi_einj new file mode 100644 index 0000000..414927b --- /dev/null +++ b/configs/config.ocp_deltalake_acpi_einj @@ -0,0 +1,3 @@ +CONFIG_VENDOR_OCP=y +CONFIG_BOARD_OCP_DELTALAKE=y +CONFIG_ACPI_EINJ=y -- To view, visit https://review.coreboot.org/c/coreboot/+/68681 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72be1c7e9f0c34c14c48cc7db69cf23d04a36366 Gerrit-Change-Number: 68681 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: util/ifdtool: Add Wellsburg support
by Patrick Rudolph (Code Review) 21 Oct '22

21 Oct '22

Attention is currently required from: Stefan Reinauer, Angel Pons. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68657 ) Change subject: util/ifdtool: Add Wellsburg support ...................................................................... Patch Set 2: (1 comment) File util/ifdtool/ifdtool.h: https://review.coreboot.org/c/coreboot/+/68657/comment/82f2aa2b_472a5b11 PS1, Line 65: PLATFORM_WLS > Wellsburg is WBG Done -- To view, visit https://review.coreboot.org/c/coreboot/+/68657 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I651730b05deb512478d059174cf8615547d2fde4 Gerrit-Change-Number: 68657 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 21 Oct 2022 18:28:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: ifdtool: Cleanup IFDv1 detection
by build bot (Jenkins) (Code Review) 21 Oct '22

21 Oct '22

Attention is currently required from: Stefan Reinauer. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68680 ) Change subject: ifdtool: Cleanup IFDv1 detection ...................................................................... Patch Set 1: (3 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161010): https://review.coreboot.org/c/coreboot/+/68680/comment/59105de5_15a537e3 PS1, Line 9: Change https://review.coreboot.org/c/coreboot/+/54305 Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161010): https://review.coreboot.org/c/coreboot/+/68680/comment/703a9135_dc0689b4 PS1, Line 11: 'agument' may be misspelled - perhaps 'argument'? Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161010): https://review.coreboot.org/c/coreboot/+/68680/comment/b6128ab7_bff0bd75 PS1, Line 13: Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/68680 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If29f8718b7aa696cdc07deef4c98be9a68c66f10 Gerrit-Change-Number: 68680 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Fri, 21 Oct 2022 18:27:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: util/ifdtool: Add Wellsburg support
by build bot (Jenkins) (Code Review) 21 Oct '22

21 Oct '22

Attention is currently required from: Patrick Rudolph, Stefan Reinauer. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68657 ) Change subject: util/ifdtool: Add Wellsburg support ...................................................................... Patch Set 2: (2 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161011): https://review.coreboot.org/c/coreboot/+/68657/comment/2c70ceec_68e0cd3b PS2, Line 23: Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Non-standard signature: Co-Developed-by: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161011): https://review.coreboot.org/c/coreboot/+/68657/comment/92fa8780_2f62804c PS2, Line 23: Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> 'Co-developed-by:' is the preferred signature form -- To view, visit https://review.coreboot.org/c/coreboot/+/68657 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I651730b05deb512478d059174cf8615547d2fde4 Gerrit-Change-Number: 68657 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Fri, 21 Oct 2022 18:27:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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