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Change subject: mb/google/brya/var/skolas: disable Tccold Handshake
......................................................................
Patch Set 3: Code-Review+2
(1 comment)
Patchset:
PS3:
Is this change required for the other RPL variants as well? (aldrvp_rpl and brya0)?
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Change subject: mb/google/brask/var/kuldax: Revise PsysPL2 to 150W for Pentium CPU
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Patch Set 3: Code-Review+2
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Change subject: soc/amd/mendocino: Add GSVCD range
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Patch Set 12:
(1 comment)
File src/soc/amd/mendocino/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/66945/comment/212d7580_806f0669
PS12, Line 332: Bootblock
> Hrmm, does verstage not verify bootblock?
Actually not since amdfw.rom (in RO/Coreboot) contains metadata hash anchor and hence is excluded from CBFS verification. Also bootblock is not signed against AMD chain of trust and hence is not verified by PSP. So it makes sense to verify the bootblock by GSC.
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Change subject: soc/amd/mendocino: Update build rules for PSP BIOS image
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Patch Set 9:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68136/comment/8140814e_e2262015
PS9, Line 9: enabled
> Can you add the reason why we don't compress. […]
When verstage runs in x86, bootblock is the first BIOS segment. Hence the metadata hash anchor is part of PSP BIOS image. If it is compressed then when a file is added to CBFS, cbfstool is not able to locate the metadata hash anchor magic and update it. Since we have sufficient space for now, I am not compressing it. We can revisit it when it requires compression.
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Change subject: soc/amd: Add an optional unsigned section in PSP verstage
......................................................................
Patch Set 9: Code-Review+2
(1 comment)
File src/soc/amd/common/block/cpu/noncar/memlayout_psp_verstage.ld:
https://review.coreboot.org/c/coreboot/+/68135/comment/93870a43_89b6468d
PS9, Line 25: ALIGN
> PSP_FOOTER_DATA already takes care of it. […]
Thanks!
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Change subject: vc/amd/fsp: Get rid of last "sabrina" reference
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Patch Set 1: Code-Review+2
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