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Change subject: mb/google/skyrim/var/baseboard: Update gpio setting for touchscreen IRQ
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Patch Set 1: Code-Review+2
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Change subject: mb/google/skyrim/var/frostflow: Update devicetree setting
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Patch Set 4:
(1 comment)
File src/mainboard/google/skyrim/variants/frostflow/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/68482/comment/12bf29b6_5ab050a4
PS3, Line 52: register "generic.probed" = "1"
> Matt is working on getting rid of this in the kernel. […]
we need to keep the probed flag for touchscreens on skyrim until CB:67778 is in (needs a re-review since I updated it). So keep for now and change all at once in CB:67779
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Change subject: soc/intel: Add node_num to dimm_info struct + adjust dimm_info_fill
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Patch Set 4: Code-Review+1
(1 comment)
File src/include/memory_info.h:
https://review.coreboot.org/c/coreboot/+/68525/comment/d0030a38_1f28dcb5
PS4, Line 96: * Node-ID / Memory-Controller-ID
> Is there any reason naming it Node-ID instead of Controller-ID? Initially I thought it meant socket […]
Alder Lake (Client) processors have 2 memory controllers in a single socket.
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Change subject: soc/amd: Add an optional unsigned section in PSP verstage
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Patch Set 9:
(1 comment)
File src/soc/amd/common/block/cpu/noncar/memlayout_psp_verstage.ld:
https://review.coreboot.org/c/coreboot/+/68135/comment/8e425ef3_a56f3a6a
PS9, Line 25: ALIGN
> Doesn't this need to move up one line if you want the anchor to be aligned to 64 bytes?
PSP_FOOTER_DATA already takes care of it. It is already starting at address that is aligned to 64 bytes and is 64 bytes in size.
Hence the anchor is already starting at an address aligned to 64 bytes. This is to ensure that the entire binary is still aligned to 64 bytes after the anchor is introduced. Anchor currently is at size 0x8c. This alignment makes it to hit 0xc0.
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Change subject: payloads/edk2: Add the recipes to assemble UniversalPayload
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Patch Set 42: Code-Review+2
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Change subject: payloads/edk2: Add the recipes to assemble UniversalPayload
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Patch Set 42:
(1 comment)
File payloads/external/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/65932/comment/af677ef3_2f165843
PS42, Line 204: CONFIG_EDK2_REPO_MRCHROMEBOX=$(CONFIG_EDK2_REPO_MRCHROMEBOX) \
> We can add them back later if still needed, but for now lets remove it first? :)
Understood now after explanation from Sean,it in there in case someone selects it, it'll error reasonably. Without it, the repo can be undefined and it just melts. Can adjust in the follow up commit. Thanks Sean
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Change subject: soc/intel/systemagent.c: Fix memory type reporting
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Patch Set 2: Code-Review+2
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Change subject: soc/intel/systemagent.c: Fix memory type reporting
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Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68405/comment/9d37d41b_d5d9ae47
PS2, Line 12:
> If you have the MTTRs before and after this change, it’d be great to see them.
Good point, I think this is resolved now as Angel has posted the log in comments.
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