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Change subject: mb/google/skyrim/var/baseboard: Update gpio setting for touchscreen IRQ
......................................................................
Patch Set 1: Code-Review+1
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Change subject: soc/amd: Add an optional unsigned section in PSP verstage
......................................................................
Patch Set 9:
(1 comment)
File src/soc/amd/common/block/cpu/noncar/memlayout_psp_verstage.ld:
https://review.coreboot.org/c/coreboot/+/68135/comment/017857f8_22d1f400
PS9, Line 25: ALIGN
Doesn't this need to move up one line if you want the anchor to be aligned to 64 bytes?
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Change subject: util/amdfwtool: Add build rules for amdfwread
......................................................................
Patch Set 11: Code-Review+2
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Change subject: util/amdfwtool/amdfwread: List AMDFW RO binary entries
......................................................................
Patch Set 13: Code-Review+2
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/66761/comment/50f9ae3a_5befb0a5
PS13, Line 20: Dir
Ohh, this is pretty
File util/amdfwtool/amdfwread.c:
https://review.coreboot.org/c/coreboot/+/66761/comment/f3e7da0b_b71c48e4
PS12, Line 330: break
> This is break for the case statement so that we dont fall-through to the next case.
Yeah.. I forgot how to read C code ;)
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Change subject: util/amdfwtool/amdfwread: Handle recovery A/B layout
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Patch Set 15: Code-Review+2
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Change subject: util/amdfwtool/amdfwread: Update relative_offset function
......................................................................
Patch Set 14: Code-Review+1
(1 comment)
File util/amdfwtool/amdfwread.c:
https://review.coreboot.org/c/coreboot/+/66572/comment/7a930e92_8084a384
PS13, Line 38: /* Intentional fall-through */
> I have to remove the check for AMD_ADDR_PHYSICAL since that check breaks the amdfwread for Guybrush […]
Ah, well glad it caught it. Maybe leave the check so it prints an error with the `exit(1)` commented out and a TODO to fix andfwtool?
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Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67917 )
Change subject: arch/x86/include: Split msr access into separate file
......................................................................
arch/x86/include: Split msr access into separate file
To allow testing of code that uses msr calls, separate the actual
calls into a separate header file, This allows the tests to emulate
the msr access without replacing the rest of the msr.h definitions.
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
Change-Id: I102709fec346f18040baf9f2ce6e6d7eb094682d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67917
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
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---
M src/include/cpu/x86/msr.h
A src/include/cpu/x86/msr_access.h
2 files changed, 82 insertions(+), 54 deletions(-)
Approvals:
build bot (Jenkins): Verified
Angel Pons: Looks good to me, approved
Jakub Czapiga: Looks good to me, approved
diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h
index ca2a37f..999fdaa 100644
--- a/src/include/cpu/x86/msr.h
+++ b/src/include/cpu/x86/msr.h
@@ -3,6 +3,8 @@
#ifndef CPU_X86_MSR_H
#define CPU_X86_MSR_H
+#include <cpu/x86/msr_access.h>
+
/* Intel SDM: Table 2-1
* IA-32 architectural MSR: Extended Feature Enable Register
*
@@ -107,66 +109,12 @@
#define IA32_CR_SF_QOS_MASK_2 0x1892
#ifndef __ASSEMBLER__
-#include <types.h>
-
-typedef struct msr_struct {
- unsigned int lo;
- unsigned int hi;
-} msr_t;
typedef struct msrinit_struct {
unsigned int index;
msr_t msr;
} msrinit_t;
-#if CONFIG(SOC_SETS_MSRS)
-msr_t soc_msr_read(unsigned int index);
-void soc_msr_write(unsigned int index, msr_t msr);
-
-/* Handle MSR references in the other source code */
-static __always_inline msr_t rdmsr(unsigned int index)
-{
- return soc_msr_read(index);
-}
-
-static __always_inline void wrmsr(unsigned int index, msr_t msr)
-{
- soc_msr_write(index, msr);
-}
-#else /* CONFIG_SOC_SETS_MSRS */
-
-/* The following functions require the __always_inline due to AMD
- * function STOP_CAR_AND_CPU that disables cache as
- * RAM, the cache as RAM stack can no longer be used. Called
- * functions must be inlined to avoid stack usage. Also, the
- * compiler must keep local variables register based and not
- * allocated them from the stack. With gcc 4.5.0, some functions
- * declared as inline are not being inlined. This patch forces
- * these functions to always be inlined by adding the qualifier
- * __always_inline to their declaration.
- */
-static __always_inline msr_t rdmsr(unsigned int index)
-{
- msr_t result;
- __asm__ __volatile__ (
- "rdmsr"
- : "=a" (result.lo), "=d" (result.hi)
- : "c" (index)
- );
- return result;
-}
-
-static __always_inline void wrmsr(unsigned int index, msr_t msr)
-{
- __asm__ __volatile__ (
- "wrmsr"
- : /* No outputs */
- : "c" (index), "a" (msr.lo), "d" (msr.hi)
- );
-}
-
-#endif /* CONFIG_SOC_SETS_MSRS */
-
/* Get MCA bank count from MSR */
static inline unsigned int mca_get_bank_count(void)
{
diff --git a/src/include/cpu/x86/msr_access.h b/src/include/cpu/x86/msr_access.h
new file mode 100644
index 0000000..a7f72fd
--- /dev/null
+++ b/src/include/cpu/x86/msr_access.h
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef CPU_X86_MSR_ACCESS_H
+#define CPU_X86_MSR_ACCESS_H
+
+#ifndef __ASSEMBLER__
+#include <types.h>
+
+typedef struct msr_struct {
+ unsigned int lo;
+ unsigned int hi;
+} msr_t;
+
+#if CONFIG(SOC_SETS_MSRS)
+msr_t soc_msr_read(unsigned int index);
+void soc_msr_write(unsigned int index, msr_t msr);
+
+/* Handle MSR references in the other source code */
+static __always_inline msr_t rdmsr(unsigned int index)
+{
+ return soc_msr_read(index);
+}
+
+static __always_inline void wrmsr(unsigned int index, msr_t msr)
+{
+ soc_msr_write(index, msr);
+}
+#else /* CONFIG_SOC_SETS_MSRS */
+
+/* The following functions require the __always_inline due to AMD
+ * function STOP_CAR_AND_CPU that disables cache as
+ * RAM, the cache as RAM stack can no longer be used. Called
+ * functions must be inlined to avoid stack usage. Also, the
+ * compiler must keep local variables register based and not
+ * allocated them from the stack. With gcc 4.5.0, some functions
+ * declared as inline are not being inlined. This patch forces
+ * these functions to always be inlined by adding the qualifier
+ * __always_inline to their declaration.
+ */
+static __always_inline msr_t rdmsr(unsigned int index)
+{
+ msr_t result;
+ __asm__ __volatile__ (
+ "rdmsr"
+ : "=a" (result.lo), "=d" (result.hi)
+ : "c" (index)
+ );
+ return result;
+}
+
+static __always_inline void wrmsr(unsigned int index, msr_t msr)
+{
+ __asm__ __volatile__ (
+ "wrmsr"
+ : /* No outputs */
+ : "c" (index), "a" (msr.lo), "d" (msr.hi)
+ );
+}
+
+#endif /* CONFIG_SOC_SETS_MSRS */
+#endif /* __ASSEMBLER__ */
+#endif /* CPU_X86_MSR_ACCESS_H */
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68588 )
Change subject: MAINTAINERS: Remove Andrey Petrov from Apollo Lake
......................................................................
MAINTAINERS: Remove Andrey Petrov from Apollo Lake
Andrey doesn't seem to have interacted with APL or coreboot
2+ years, so remove him and mark Apollo Lake as orphaned.
Add myself for Odd Fixes.
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
Change-Id: I6cb2f2da63dda3cb841786d53f89b583a9df9791
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68588
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Andrey Petrov <andrey.petrov(a)gmail.com>
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
---
M MAINTAINERS
1 file changed, 21 insertions(+), 2 deletions(-)
Approvals:
build bot (Jenkins): Verified
Andrey Petrov: Looks good to me, but someone else must approve
Angel Pons: Looks good to me, approved
diff --git a/MAINTAINERS b/MAINTAINERS
index a564e14..dc4c3af 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -723,8 +723,8 @@
F: src/soc/intel/alderlake/
INTEL APOLLOLAKE_SOC
-M: Andrey Petrov <andrey.petrov(a)gmail.com>
-S: Maintained
+M: Sean Rhodes <sean(a)starlabs.systems>
+S: Odd Fixes
F: src/soc/intel/apollolake/
INTEL BRASWELL SOC
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