coreboot-gerrit October 2022

coreboot-gerrit@coreboot.org

1 participants
5881 discussions

[M] Change in coreboot[master]: soc/mediatek: Unify PLL function names
by Felix Held (Code Review) 21 Oct '22

21 Oct '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68622 ) ( 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/mediatek: Unify PLL function names ...................................................................... soc/mediatek: Unify PLL function names For consistency with the PLL function naming: - Rename edp_mux_set_sel() to mt_pll_edp_mux_set_sel(). - Rename mux_set_sel() to pll_mux_set_sel(). BUG=none TEST=build pass. BRANCH=corsola Signed-off-by: Bo-Chen Chen <rex-bc.chen(a)mediatek.com> Change-Id: Ifc7b14bf0db5a5461037e2fbf41756d1542ca945 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68622 Reviewed-by: Yidi Lin <yidilin(a)google.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/common/include/soc/pll_common.h M src/soc/mediatek/common/pll.c M src/soc/mediatek/mt8173/pll.c M src/soc/mediatek/mt8183/pll.c M src/soc/mediatek/mt8186/pll.c M src/soc/mediatek/mt8188/pll.c M src/soc/mediatek/mt8192/pll.c M src/soc/mediatek/mt8195/dp_intf.c M src/soc/mediatek/mt8195/pll.c 9 files changed, 41 insertions(+), 16 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, but someone else must approve diff --git a/src/soc/mediatek/common/include/soc/pll_common.h b/src/soc/mediatek/common/include/soc/pll_common.h index 5c73a12..5484d67 100644 --- a/src/soc/mediatek/common/include/soc/pll_common.h +++ b/src/soc/mediatek/common/include/soc/pll_common.h @@ -64,14 +64,17 @@ DEFINE_BITFIELD(PLL_CON1, 31, 0) +/* PLL internal interface */ void pll_set_pcw_change(const struct pll *pll); -void mux_set_sel(const struct mux *mux, u32 sel); +void pll_mux_set_sel(const struct mux *mux, u32 sel); int pll_set_rate(const struct pll *pll, u32 rate); + +/* PLL internal interface */ void mt_pll_init(void); void mt_pll_raise_little_cpu_freq(u32 freq); void mt_pll_raise_cci_freq(u32 freq); void mt_pll_set_tvd_pll1_freq(u32 freq); -void edp_mux_set_sel(u32 sel); +void mt_pll_edp_mux_set_sel(u32 sel); void mt_pll_spmi_mux_select(void); void mt_pll_set_usb_clock(void); diff --git a/src/soc/mediatek/common/pll.c b/src/soc/mediatek/common/pll.c index ca6226a..f13911b 100644 --- a/src/soc/mediatek/common/pll.c +++ b/src/soc/mediatek/common/pll.c @@ -5,7 +5,7 @@ #include <soc/pll.h> #include <types.h> -void mux_set_sel(const struct mux *mux, u32 sel) +void pll_mux_set_sel(const struct mux *mux, u32 sel) { u32 mask = GENMASK(mux->mux_width - 1, 0); u32 val = read32(mux->reg); diff --git a/src/soc/mediatek/mt8173/pll.c b/src/soc/mediatek/mt8173/pll.c index 7133fde..bbbb1f3 100644 --- a/src/soc/mediatek/mt8173/pll.c +++ b/src/soc/mediatek/mt8173/pll.c @@ -347,7 +347,7 @@ * TOP CLKMUX -- DO NOT CHANGE WITHOUT ADJUSTING <soc/pll.h> CONSTANTS! *************/ for (i = 0; i < ARRAY_SIZE(mux_sels); i++) - mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel); + pll_mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel); /* enable scpsys clock off control */ write32(&mtk_topckgen->clk_scp_cfg_0, @@ -445,5 +445,5 @@ void mt_mem_pll_mux(void) { /* CLK_CFG_0 */ - mux_set_sel(&muxes[TOP_MEM_SEL], 1); /* 1: dmpll_ck */ + pll_mux_set_sel(&muxes[TOP_MEM_SEL], 1); /* 1: dmpll_ck */ } diff --git a/src/soc/mediatek/mt8183/pll.c b/src/soc/mediatek/mt8183/pll.c index 0e96f4c..87562b1 100644 --- a/src/soc/mediatek/mt8183/pll.c +++ b/src/soc/mediatek/mt8183/pll.c @@ -344,7 +344,7 @@ * TOP CLKMUX -- DO NOT CHANGE WITHOUT ADJUSTING <soc/pll.h> CONSTANTS! */ for (i = 0; i < ARRAY_SIZE(mux_sels); i++) - mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel); + pll_mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel); /* enable [14] dramc_pll104m_ck */ setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 14); diff --git a/src/soc/mediatek/mt8186/pll.c b/src/soc/mediatek/mt8186/pll.c index 9ab4f9c..a6165ef 100644 --- a/src/soc/mediatek/mt8186/pll.c +++ b/src/soc/mediatek/mt8186/pll.c @@ -468,7 +468,7 @@ INFRACFG_AO_PERI_BUS_REG0_2, 1); for (i = 0; i < ARRAY_SIZE(mux_sels); i++) - mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel); + pll_mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel); /* [4] SCP_CORE_CK_CG, [5] SEJ_CG */ write32(&mt8186_infracfg_ao->module_sw_cg_0_clr, 0x00000030); @@ -528,7 +528,7 @@ void mt_pll_spmi_mux_select(void) { /* 4: ulposc1_d10 */ - mux_set_sel(&muxes[TOP_SPMI_MST_SEL], 4); + pll_mux_set_sel(&muxes[TOP_SPMI_MST_SEL], 4); } u32 mt_fmeter_get_freq_khz(enum fmeter_type type, u32 id) diff --git a/src/soc/mediatek/mt8188/pll.c b/src/soc/mediatek/mt8188/pll.c index e88c192..a519fdd 100644 --- a/src/soc/mediatek/mt8188/pll.c +++ b/src/soc/mediatek/mt8188/pll.c @@ -573,7 +573,7 @@ * TOP CLKMUX -- DO NOT CHANGE WITHOUT ADJUSTING <soc/pll.h> CONSTANTS! */ for (i = 0; i < ARRAY_SIZE(mux_sels); i++) - mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel); + pll_mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel); /* turn off unused clock in infra_ao */ write32(&mt8188_infracfg_ao->module_sw_cg_1_set, 0x00004000); @@ -633,9 +633,9 @@ udelay(PLL_EN_DELAY); } -void edp_mux_set_sel(u32 sel) +void mt_pll_edp_mux_set_sel(u32 sel) { - mux_set_sel(&muxes[TOP_EDP_SEL], sel); + pll_mux_set_sel(&muxes[TOP_EDP_SEL], sel); } void mt_pll_set_usb_clock(void) diff --git a/src/soc/mediatek/mt8192/pll.c b/src/soc/mediatek/mt8192/pll.c index c9e2753..432b192 100644 --- a/src/soc/mediatek/mt8192/pll.c +++ b/src/soc/mediatek/mt8192/pll.c @@ -464,7 +464,7 @@ * TOP CLKMUX -- DO NOT CHANGE WITHOUT ADJUSTING <soc/pll.h> CONSTANTS! */ for (i = 0; i < ARRAY_SIZE(mux_sels); i++) - mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel); + pll_mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel); /* enable [14] dramc_pll104m_ck */ setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 14); diff --git a/src/soc/mediatek/mt8195/dp_intf.c b/src/soc/mediatek/mt8195/dp_intf.c index 69a7740..ab2070e 100644 --- a/src/soc/mediatek/mt8195/dp_intf.c +++ b/src/soc/mediatek/mt8195/dp_intf.c @@ -221,7 +221,7 @@ pll_rate = edid->mode.pixel_clock * 1000 * (1 << ((clksrc + 1) / 2)); mt_pll_set_tvd_pll1_freq(pll_rate / 4); - edp_mux_set_sel(clksrc); + mt_pll_edp_mux_set_sel(clksrc); mtk_dpintf_enable(dpintf); diff --git a/src/soc/mediatek/mt8195/pll.c b/src/soc/mediatek/mt8195/pll.c index 06b2156..792af7f 100644 --- a/src/soc/mediatek/mt8195/pll.c +++ b/src/soc/mediatek/mt8195/pll.c @@ -755,7 +755,7 @@ * TOP CLKMUX -- DO NOT CHANGE WITHOUT ADJUSTING <soc/pll.h> CONSTANTS! */ for (i = 0; i < ARRAY_SIZE(mux_sels); i++) - mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel); + pll_mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel); /* switch sram control to bypass mode for PCIE_MAC_P0 */ setbits32(&mtk_spm->ap_mdsrc_req, 0x1); @@ -827,9 +827,9 @@ udelay(PLL_EN_DELAY); } -void edp_mux_set_sel(u32 sel) +void mt_pll_edp_mux_set_sel(u32 sel) { - mux_set_sel(&muxes[TOP_EDP_SEL], sel); + pll_mux_set_sel(&muxes[TOP_EDP_SEL], sel); } u32 mt_fmeter_get_freq_khz(enum fmeter_type type, u32 id) -- To view, visit https://review.coreboot.org/c/coreboot/+/68622 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc7b14bf0db5a5461037e2fbf41756d1542ca945 Gerrit-Change-Number: 68622 Gerrit-PatchSet: 7 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: mb/google/corsola: Initialize MT6315 for MT8186T
by Felix Held (Code Review) 21 Oct '22

21 Oct '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68621 ) ( 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/corsola: Initialize MT6315 for MT8186T ...................................................................... mb/google/corsola: Initialize MT6315 for MT8186T Initialize MT6315 for powering on big cores on MT8186T. BUG=b:249436110 TEST=build pass. BRANCH=corsola Signed-off-by: Sen Chu <sen.chu(a)mediatek.corp-partner.google.com> Signed-off-by: Bo-Chen Chen <rex-bc.chen(a)mediatek.com> Change-Id: Ib1d71d4f1689ba1e7ea5f798503ef11eff423fff Reviewed-on: https://review.coreboot.org/c/coreboot/+/68621 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/corsola/romstage.c 1 file changed, 30 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/corsola/romstage.c b/src/mainboard/google/corsola/romstage.c index 01f8af3..1dc6a22 100644 --- a/src/mainboard/google/corsola/romstage.c +++ b/src/mainboard/google/corsola/romstage.c @@ -3,9 +3,12 @@ #include <arch/stages.h> #include <console/console.h> #include <delay.h> +#include <soc/cpu_id.h> #include <soc/emi.h> +#include <soc/mt6315.h> #include <soc/mt6366.h> #include <soc/pll_common.h> +#include <soc/pmif.h> #include <soc/regulator.h> #include <soc/rtc.h> @@ -27,5 +30,11 @@ mt6366_init(); raise_little_cpu_freq(); rtc_boot(); + + if (get_cpu_id() == MTK_CPU_ID_MT8186T) { + mtk_pmif_init(); + mt6315_init(); + } + mtk_dram_init(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/68621 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib1d71d4f1689ba1e7ea5f798503ef11eff423fff Gerrit-Change-Number: 68621 Gerrit-PatchSet: 6 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[L] Change in coreboot[master]: soc/mediatek/mt8186: Add support for PMIC MT6315
by Felix Held (Code Review) 21 Oct '22

21 Oct '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68620 ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/mediatek/mt8186: Add support for PMIC MT6315 ...................................................................... soc/mediatek/mt8186: Add support for PMIC MT6315 On MT8186T, the big cores are powered on by MT6315 via PMIF. This patch adds the following changes. - Add MT6315 settings. - Configure PMIC PMIF for MT6315. BUG=b:249436110 TEST=build pass. BRANCH=corsola Signed-off-by: Sen Chu <sen.chu(a)mediatek.corp-partner.google.com> Signed-off-by: Bo-Chen Chen <rex-bc.chen(a)mediatek.com> Change-Id: Id01931e564b0b5002b8d6b9d13d4f32cdf0ae708 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68620 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/common/include/soc/pll_common.h M src/soc/mediatek/mt8186/Makefile.inc M src/soc/mediatek/mt8186/include/soc/addressmap.h M src/soc/mediatek/mt8186/include/soc/pll.h M src/soc/mediatek/mt8186/include/soc/pmif.h A src/soc/mediatek/mt8186/mt6315.c M src/soc/mediatek/mt8186/pll.c M src/soc/mediatek/mt8186/pmif.c A src/soc/mediatek/mt8186/pmif_clk.c A src/soc/mediatek/mt8186/pmif_spmi.c 10 files changed, 398 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, but someone else must approve diff --git a/src/soc/mediatek/common/include/soc/pll_common.h b/src/soc/mediatek/common/include/soc/pll_common.h index 6eac8b2..5c73a12 100644 --- a/src/soc/mediatek/common/include/soc/pll_common.h +++ b/src/soc/mediatek/common/include/soc/pll_common.h @@ -72,6 +72,7 @@ void mt_pll_raise_cci_freq(u32 freq); void mt_pll_set_tvd_pll1_freq(u32 freq); void edp_mux_set_sel(u32 sel); +void mt_pll_spmi_mux_select(void); void mt_pll_set_usb_clock(void); enum fmeter_type { diff --git a/src/soc/mediatek/mt8186/Makefile.inc b/src/soc/mediatek/mt8186/Makefile.inc index c8dbbc9..5764634 100644 --- a/src/soc/mediatek/mt8186/Makefile.inc +++ b/src/soc/mediatek/mt8186/Makefile.inc @@ -25,7 +25,10 @@ romstage-y += ../common/memory.c romstage-y += ../common/memory_test.c romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c +romstage-y += ../common/mt6315.c mt6315.c romstage-y += ../common/pmic_wrap.c pmic_wrap.c pmif.c mt6366.c +romstage-y += ../common/pmif.c ../common/pmif_clk.c pmif_clk.c +romstage-y += ../common/pmif_spmi.c pmif_spmi.c romstage-y += ../common/rtc.c ../common/rtc_osc_init.c rtc.c ramstage-y += adsp.c diff --git a/src/soc/mediatek/mt8186/include/soc/addressmap.h b/src/soc/mediatek/mt8186/include/soc/addressmap.h index 33a2327..5f0b10c 100644 --- a/src/soc/mediatek/mt8186/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8186/include/soc/addressmap.h @@ -29,10 +29,14 @@ EINT_BASE = IO_PHYS + 0x0000B000, APMIXED_BASE = IO_PHYS + 0x0000C000, PWRAP_BASE = IO_PHYS + 0x0000D000, + /* Add PMICSPI_MST_BASE and PMIF_SPI_BASE to solve the build error */ + PMICSPI_MST_BASE = IO_PHYS + 0x0000D000, + PMIF_SPI_BASE = IO_PHYS + 0x0000D000, DEVAPC_AO_INFRA_PERI_BASE = IO_PHYS + 0x0000E000, DEVAPC_AO_MM_BASE = IO_PHYS + 0x0000F000, - PMIF_BASE = IO_PHYS + 0x00015000, + PMIF_SPMI_BASE = IO_PHYS + 0x00015000, SYSTIMER_BASE = IO_PHYS + 0x00017000, + SPMI_MST_BASE = IO_PHYS + 0x0001B000, I2C0_DMA_BASE = IO_PHYS + 0x00200100, I2C1_DMA_BASE = IO_PHYS + 0x00200200, I2C2_DMA_BASE = IO_PHYS + 0x00200300, @@ -50,6 +54,7 @@ DRAMC_CHA_AO_BASE = IO_PHYS + 0x00220000, SSPM_SRAM_BASE = IO_PHYS + 0x00400000, SSPM_CFG_BASE = IO_PHYS + 0x00440000, + SCP_CLK_BASE = IO_PHYS + 0x005C4000, AUDIODSP_BASE = IO_PHYS + 0x00680000, DEVAPC_AO_AUD_BASE = IO_PHYS + 0x0069C000, SFLASH_REG_BASE = IO_PHYS + 0x01000000, diff --git a/src/soc/mediatek/mt8186/include/soc/pll.h b/src/soc/mediatek/mt8186/include/soc/pll.h index bcd00da..8df7f96 100644 --- a/src/soc/mediatek/mt8186/include/soc/pll.h +++ b/src/soc/mediatek/mt8186/include/soc/pll.h @@ -16,7 +16,8 @@ u32 clk_mode; u32 clk_cfg_update; u32 clk_cfg_update1; - u32 reserved1[13]; + u32 clk_cfg_update2; + u32 reserved1[12]; u32 clk_cfg_0; u32 clk_cfg_0_set; u32 clk_cfg_0_clr; @@ -117,6 +118,7 @@ check_member(mtk_topckgen_regs, clk_mode, 0x0); check_member(mtk_topckgen_regs, clk_cfg_update, 0x4); check_member(mtk_topckgen_regs, clk_cfg_update1, 0x8); +check_member(mtk_topckgen_regs, clk_cfg_update2, 0xc); check_member(mtk_topckgen_regs, clk_cfg_0, 0x40); check_member(mtk_topckgen_regs, clk_cfg_0_set, 0x44); check_member(mtk_topckgen_regs, clk_cfg_0_clr, 0x48); diff --git a/src/soc/mediatek/mt8186/include/soc/pmif.h b/src/soc/mediatek/mt8186/include/soc/pmif.h index 0e1e1a2..2eecb26 100644 --- a/src/soc/mediatek/mt8186/include/soc/pmif.h +++ b/src/soc/mediatek/mt8186/include/soc/pmif.h @@ -8,9 +8,142 @@ #ifndef __SOC_MEDIATEK_MT8186_PMIF_H__ #define __SOC_MEDIATEK_MT8186_PMIF_H__ +#include <device/mmio.h> #include <soc/addressmap.h> +#include <soc/pmif_common.h> #include <types.h> +/* indicate which number SW channel start, by project */ +#define PMIF_SPMI_SW_CHAN 0xFFFFFFFF +#define PMIF_SPMI_INF 0xFFFFFFFF + +struct mtk_pmif_regs { + u32 init_done; + u32 reserved1[5]; + u32 inf_busy_sta; + u32 other_busy_sta_0; + u32 other_busy_sta_1; + u32 inf_en; + u32 other_inf_en; + u32 inf_cmd_per_0; + u32 inf_cmd_per_1; + u32 inf_cmd_per_2; + u32 inf_cmd_per_3; + u32 inf_max_bytecnt_per_0; + u32 inf_max_bytecnt_per_1; + u32 inf_max_bytecnt_per_2; + u32 inf_max_bytecnt_per_3; + u32 staupd_ctrl; + u32 reserved2[48]; + u32 int_gps_auxadc_cmd_addr; + u32 int_gps_auxadc_cmd; + u32 int_gps_auxadc_rdata_addr; + u32 reserved3[13]; + u32 arb_en; + u32 reserved4[34]; + u32 lat_cnter_ctrl; + u32 lat_cnter_en; + u32 lat_limit_loading; + u32 lat_limit_0; + u32 lat_limit_1; + u32 lat_limit_2; + u32 lat_limit_3; + u32 lat_limit_4; + u32 lat_limit_5; + u32 lat_limit_6; + u32 lat_limit_7; + u32 lat_limit_8; + u32 lat_limit_9; + u32 reserved5[99]; + u32 crc_ctrl; + u32 crc_sta; + u32 sig_mode; + u32 pmic_sig_addr; + u32 pmic_sig_val; + u32 reserved6[2]; + u32 cmdissue_en; + u32 reserved7[10]; + u32 timer_ctrl; + u32 timer_sta; + u32 sleep_protection_ctrl; + u32 reserved8[6]; + u32 spi_mode_ctrl; + u32 reserved9[2]; + u32 pmic_eint_sta_addr; + u32 reserved10[2]; + u32 irq_event_en_0; + u32 irq_flag_raw_0; + u32 irq_flag_0; + u32 irq_clr_0; + u32 reserved11[244]; + u32 swinf_0_acc; + u32 swinf_0_wdata_31_0; + u32 swinf_0_wdata_63_32; + u32 reserved12[2]; + u32 swinf_0_rdata_31_0; + u32 swinf_0_rdata_63_32; + u32 reserved13[2]; + u32 swinf_0_vld_clr; + u32 swinf_0_sta; + u32 reserved14[5]; + u32 swinf_1_acc; + u32 swinf_1_wdata_31_0; + u32 swinf_1_wdata_63_32; + u32 reserved15[2]; + u32 swinf_1_rdata_31_0; + u32 swinf_1_rdata_63_32; + u32 reserved16[2]; + u32 swinf_1_vld_clr; + u32 swinf_1_sta; + u32 reserved17[5]; + u32 swinf_2_acc; + u32 swinf_2_wdata_31_0; + u32 swinf_2_wdata_63_32; + u32 reserved18[2]; + u32 swinf_2_rdata_31_0; + u32 swinf_2_rdata_63_32; + u32 reserved19[2]; + u32 swinf_2_vld_clr; + u32 swinf_2_sta; + u32 reserved20[5]; + u32 swinf_3_acc; + u32 swinf_3_wdata_31_0; + u32 swinf_3_wdata_63_32; + u32 reserved21[2]; + u32 swinf_3_rdata_31_0; + u32 swinf_3_rdata_63_32; + u32 reserved22[2]; + u32 swinf_3_vld_clr; + u32 swinf_3_sta; + u32 reserved23[133]; +}; +check_member(mtk_pmif_regs, inf_busy_sta, 0x18); +check_member(mtk_pmif_regs, int_gps_auxadc_cmd_addr, 0x110); +check_member(mtk_pmif_regs, arb_en, 0x0150); +check_member(mtk_pmif_regs, lat_cnter_en, 0x1E0); +check_member(mtk_pmif_regs, crc_ctrl, 0x39C); +check_member(mtk_pmif_regs, cmdissue_en, 0x3B8); +check_member(mtk_pmif_regs, timer_ctrl, 0x3E4); +check_member(mtk_pmif_regs, spi_mode_ctrl, 0x408); +check_member(mtk_pmif_regs, pmic_eint_sta_addr, 0x414); +check_member(mtk_pmif_regs, irq_event_en_0, 0x420); +check_member(mtk_pmif_regs, swinf_0_acc, 0x800); + +#define PMIF_SPMI_AP_CHAN (PMIF_SPMI_BASE + 0x880) +#define PMIF_SPI_AP_CHAN (PMIF_SPI_BASE + 0xC20) + +enum { + FREQ_250MHZ = 250, +}; + +struct mtk_scp_clk_regs { + u32 reserved0; + u32 scp_clk_en; +}; +check_member(mtk_scp_clk_regs, scp_clk_en, 0x4); + +#define mtk_scp_clk ((struct mtk_scp_clk_regs *)SCP_CLK_BASE) + void pmif_spmi_set_lp_mode(void); #endif /*__SOC_MEDIATEK_MT8186_PMIF_H__*/ diff --git a/src/soc/mediatek/mt8186/mt6315.c b/src/soc/mediatek/mt8186/mt6315.c new file mode 100644 index 0000000..1e6f035 --- /dev/null +++ b/src/soc/mediatek/mt8186/mt6315.c @@ -0,0 +1,108 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#include <soc/mt6315.h> + +/* + * These values are used by MediaTek internally. + * We can find these registers in "MT6315 datasheet v1.3.pdf". + * The setting values are provided by MeidaTek designers. + */ + +static const struct mt6315_setting init_setting_cpu[] = { + /* remove protection */ + {0x3A9, 0x63, 0xFF, 0}, + {0x3A8, 0x15, 0xFF, 0}, + {0x3A0, 0x9C, 0xFF, 0}, + {0x39F, 0xEA, 0xFF, 0}, + {0x993, 0x47, 0xFF, 0}, + {0x992, 0x29, 0xFF, 0}, + {0x1418, 0x55, 0xFF, 0}, + {0x1417, 0x43, 0xFF, 0}, + {0x3A2, 0x2A, 0xFF, 0}, + {0x3A1, 0x7C, 0xFF, 0}, + /* init settings for mt6315 */ + {0x997, 0xF, 0x7F, 0}, + {0x999, 0xF0, 0xF0, 0}, + {0x9A0, 0x0, 0x1F, 0}, + {0x9A1, 0x0, 0x1F, 0}, + {0x9A2, 0x0, 0x1F, 0}, + {0x9A3, 0x0, 0x1F, 0}, + {0x1440, 0x0, 0xE, 0}, + {0x1487, 0x58, 0xFF, 0}, + {0x148B, 0x3, 0x7F, 0}, + {0x148C, 0x3, 0x7F, 0}, + {0x1507, 0x58, 0xFF, 0}, + {0x150B, 0x3, 0x7F, 0}, + {0x150C, 0x3, 0x7F, 0}, + {0x1587, 0x58, 0xFF, 0}, + {0x158B, 0x3, 0x7F, 0}, + {0x158C, 0x3, 0x7F, 0}, + {0x1607, 0x58, 0xFF, 0}, + {0x160B, 0x3, 0x7F, 0}, + {0x160C, 0x3, 0x7F, 0}, + {0x1687, 0x22, 0x76, 0}, + {0x1688, 0xF, 0x2F, 0}, + {0x1689, 0xA1, 0xE1, 0}, + {0x168A, 0x79, 0x7F, 0}, + {0x168B, 0x12, 0x3F, 0}, + {0x168D, 0xC, 0xC, 0}, + {0x168E, 0xD7, 0xFF, 0}, + {0x168F, 0x81, 0xFF, 0}, + {0x1690, 0x3, 0x3F, 0}, + {0x1691, 0x22, 0x76, 0}, + {0x1692, 0xF, 0x2F, 0}, + {0x1693, 0xA1, 0xE1, 0}, + {0x1694, 0x79, 0x7F, 0}, + {0x1695, 0x12, 0x3F, 0}, + {0x1697, 0xC, 0xC, 0}, + {0x1698, 0xD7, 0xFF, 0}, + {0x1699, 0x81, 0xFF, 0}, + {0x169A, 0x3, 0x3F, 0}, + {0x169B, 0x22, 0x76, 0}, + {0x169C, 0xF, 0x2F, 0}, + {0x169D, 0xA1, 0xE1, 0}, + {0x169E, 0x79, 0xFF, 0}, + {0x169F, 0x12, 0x3F, 0}, + {0x16A1, 0xC, 0xC, 0}, + {0x16A2, 0xD7, 0xFF, 0}, + {0x16A3, 0x81, 0xFF, 0}, + {0x16A4, 0x3, 0x3F, 0}, + {0x16A5, 0x22, 0x76, 0}, + {0x16A6, 0xF, 0x2F, 0}, + {0x16A7, 0xA1, 0xE1, 0}, + {0x16A8, 0x79, 0xFF, 0}, + {0x16A9, 0x12, 0x3F, 0}, + {0x16AB, 0xC, 0xC, 0}, + {0x16AC, 0xD7, 0xFF, 0}, + {0x16AD, 0x81, 0xFF, 0}, + {0x16AE, 0x3, 0x3F, 0}, + {0x16CE, 0x0, 0x8, 0}, + {0x13, 0x2, 0x2, 0}, + {0x15, 0x1F, 0x1F, 0}, + {0x22, 0x12, 0x12, 0}, + {0x8A, 0x6, 0xF, 0}, + {0x10B, 0x3, 0x3, 0}, + {0x38B, 0x4, 0xFF, 0}, + {0xA07, 0x0, 0x1, 0}, + {0xA1A, 0x1F, 0x1F, 0}, + {0x1457, 0x0, 0xFF, 0}, + /* add protection */ + {0x3A1, 0x0, 0xFF, 0}, + {0x3A2, 0x0, 0xFF, 0}, + {0x1417, 0x0, 0xFF, 0}, + {0x1418, 0x0, 0xFF, 0}, + {0x992, 0x0, 0xFF, 0}, + {0x993, 0x0, 0xFF, 0}, + {0x39F, 0x0, 0xFF, 0}, + {0x3A0, 0x0, 0xFF, 0}, + {0x3A8, 0x0, 0xFF, 0}, + {0x3A9, 0x0, 0xFF, 0}, +}; + +void mt6315_init_setting(void) +{ + for (int i = 0; i < ARRAY_SIZE(init_setting_cpu); i++) + mt6315_write_field(MT6315_CPU, + init_setting_cpu[i].addr, init_setting_cpu[i].val, + init_setting_cpu[i].mask, init_setting_cpu[i].shift); +} diff --git a/src/soc/mediatek/mt8186/pll.c b/src/soc/mediatek/mt8186/pll.c index 9d8343b..9ab4f9c 100644 --- a/src/soc/mediatek/mt8186/pll.c +++ b/src/soc/mediatek/mt8186/pll.c @@ -525,6 +525,12 @@ SET32_BITFIELDS(&mtk_topckgen->usb_top_cfg, USB_TOP_CFG_MACRO_CTRL, 3); } +void mt_pll_spmi_mux_select(void) +{ + /* 4: ulposc1_d10 */ + mux_set_sel(&muxes[TOP_SPMI_MST_SEL], 4); +} + u32 mt_fmeter_get_freq_khz(enum fmeter_type type, u32 id) { u32 output, count, clk_dbg_cfg, clk_misc_cfg_0, clk26cali_0, clk26cali_1; diff --git a/src/soc/mediatek/mt8186/pmif.c b/src/soc/mediatek/mt8186/pmif.c index b909609..c1a9bcc 100644 --- a/src/soc/mediatek/mt8186/pmif.c +++ b/src/soc/mediatek/mt8186/pmif.c @@ -15,7 +15,7 @@ void pmif_spmi_set_lp_mode(void) { - SET32_BITFIELDS((void *)(PMIF_BASE + SLEEP_PROT_CTRL), + SET32_BITFIELDS((void *)(PMIF_SPMI_BASE + SLEEP_PROT_CTRL), SPM_SLEEP_REQ_SEL, 0, SCP_SLEEP_REQ_SEL, 0); } diff --git a/src/soc/mediatek/mt8186/pmif_clk.c b/src/soc/mediatek/mt8186/pmif_clk.c new file mode 100644 index 0000000..4cdc710 --- /dev/null +++ b/src/soc/mediatek/mt8186/pmif_clk.c @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#include <console/console.h> +#include <delay.h> +#include <device/mmio.h> +#include <soc/pll.h> +#include <soc/pll_common.h> +#include <soc/pmif.h> +#include <soc/pmif_clk_common.h> +#include <soc/pmif_sw.h> + +#define FREQ_METER_ABIST_AD_OSC_CK 35 + +#define SCP_CLK_SRC BIT(1) +#define SCP_CLK_CG BIT(2) + +#define ULPOSC1_RG_OSC_DIV BIT(18) + +#define ULPOSC1_CALI_HW_MODE (BIT(16) | BIT(17)) +#define ULPOSC1_ENABLE_SW_MODE (BIT(18) | BIT(19)) + +u32 pmif_get_ulposc_freq_mhz(u32 cali_val) +{ + u32 result; + + clrsetbits32(&mtk_apmixed->ap_pll_con0, ULPOSC1_CALI_HW_MODE, ULPOSC1_ENABLE_SW_MODE); + clrbits32(&mtk_apmixed->ulposc_con0, cali_val); + + /* enable ulposc1 */ + setbits32(&mtk_scp_clk->scp_clk_en, SCP_CLK_SRC); + udelay(150); + setbits32(&mtk_scp_clk->scp_clk_en, SCP_CLK_CG); + + result = mt_fmeter_get_freq_khz(FMETER_ABIST, FREQ_METER_ABIST_AD_OSC_CK); + + return result / 1000; +} + +int pmif_clk_init(void) +{ + u32 ulposc; + + /* get hardware default value */ + ulposc = pmif_get_ulposc_freq_mhz(ULPOSC1_RG_OSC_DIV); + if (pmif_ulposc_check(ulposc, FREQ_250MHZ)) + die("ERROR: failed to meet ulposc frequency\n"); + + mt_pll_spmi_mux_select(); + + return 0; +} diff --git a/src/soc/mediatek/mt8186/pmif_spmi.c b/src/soc/mediatek/mt8186/pmif_spmi.c new file mode 100644 index 0000000..28ea739 --- /dev/null +++ b/src/soc/mediatek/mt8186/pmif_spmi.c @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#include <device/mmio.h> +#include <soc/pll.h> +#include <soc/pmif_spmi.h> +#include <console/console.h> + +/* IOCFG_LT, DRV_CFG2 */ +DEFINE_BITFIELD(SPMI_SCL, 14, 12) +DEFINE_BITFIELD(SPMI_SDA, 17, 15) +DEFINE_BIT(SPMI_SCL_IN, 27) +DEFINE_BIT(SPMI_SDA_IN, 28) +DEFINE_BIT(SPMI_SCL_PU, 11) +DEFINE_BIT(SPMI_SDA_PD, 12) +DEFINE_BIT(SPMI_SCL_SMT, 28) +DEFINE_BIT(SPMI_SDA_SMT, 28) +DEFINE_BITFIELD(SPMI_TD, 19, 16) +DEFINE_BITFIELD(SPMI_RD, 15, 14) +DEFINE_BITFIELD(SPMI_DRI, 5, 3) + +/* TOPRGU, WDT_SWSYSRST2 */ +DEFINE_BIT(SPMI_MST_RST, 23) +DEFINE_BITFIELD(UNLOCK_KEY, 31, 24) + +/* TOPCKGEN, CLK_CFG_17 */ +DEFINE_BITFIELD(CLK_SPMI_MST_SEL, 10, 8) +DEFINE_BIT(CLK_SPMI_MST_INT, 12) +DEFINE_BIT(PDN_SPMI_MST, 15) + +/* TOPCKGEN, CLK_CFG_UPDATE2 */ +DEFINE_BIT(SPMI_MST_CK_UPDATE, 5) + +const struct spmi_device spmi_dev[] = { + { + .slvid = SPMI_SLAVE_6, + .type = BUCK_CPU, + .type_id = BUCK_CPU_ID, + }, +}; + +const size_t spmi_dev_cnt = ARRAY_SIZE(spmi_dev); + +int spmi_config_master(void) +{ + /* Software reset */ + SET32_BITFIELDS(&mtk_rug->wdt_swsysrst2, SPMI_MST_RST, 1, UNLOCK_KEY, 0x88); + + SET32_BITFIELDS(&mtk_topckgen->clk_cfg_11, + CLK_SPMI_MST_SEL, 0x3, + CLK_SPMI_MST_INT, 0, + PDN_SPMI_MST, 0); + SET32_BITFIELDS(&mtk_topckgen->clk_cfg_update2, SPMI_MST_CK_UPDATE, 1); + + /* Software reset */ + SET32_BITFIELDS(&mtk_rug->wdt_swsysrst2, SPMI_MST_RST, 0, UNLOCK_KEY, 0x88); + + /* Enable SPMI */ + write32(&mtk_spmi_mst->mst_req_en, 1); + write32(&mtk_spmi_mst->rcs_ctrl, 0x15); + + return 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/68620 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id01931e564b0b5002b8d6b9d13d4f32cdf0ae708 Gerrit-Change-Number: 68620 Gerrit-PatchSet: 5 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[master]: soc/mediatek: Move SPMI interface configuration to SoC folder
by Felix Held (Code Review) 21 Oct '22

21 Oct '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68619 ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/mediatek: Move SPMI interface configuration to SoC folder ...................................................................... soc/mediatek: Move SPMI interface configuration to SoC folder The SPMI interface configuration is SoC-dependent. - MT8192 and MT8195 are the same. - MT8186 does not need to implement this. - MT8188 is different from MT8195, and we will submit another patch to fix this. BUG=b:249436110 TEST=build pass. BRANCH=corsola Signed-off-by: Sen Chu <sen.chu(a)mediatek.corp-partner.google.com> Signed-off-by: Bo-Chen Chen <rex-bc.chen(a)mediatek.com> Change-Id: I4cf508a0690995a7fe7b7316269d07cb7a799191 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68619 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/common/include/soc/pmif_spmi.h M src/soc/mediatek/common/pmif_spmi.c M src/soc/mediatek/mt8188/pmif_spmi.c M src/soc/mediatek/mt8192/pmif_spmi.c M src/soc/mediatek/mt8195/pmif_spmi.c 5 files changed, 98 insertions(+), 19 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, but someone else must approve diff --git a/src/soc/mediatek/common/include/soc/pmif_spmi.h b/src/soc/mediatek/common/include/soc/pmif_spmi.h index 0f79ad4e..d970e59 100644 --- a/src/soc/mediatek/common/include/soc/pmif_spmi.h +++ b/src/soc/mediatek/common/include/soc/pmif_spmi.h @@ -10,6 +10,9 @@ #define DEFAULT_VALUE_READ_TEST (0x5a) #define DEFAULT_VALUE_WRITE_TEST (0xa5) +#define PMIF_CMD_PER_3 (0x1 << PMIF_CMD_EXT_REG_LONG) +#define PMIF_CMD_PER_1_3 ((0x1 << PMIF_CMD_REG) | (0x1 << PMIF_CMD_EXT_REG_LONG)) + struct mtk_rgu_regs { u32 reserved[36]; u32 wdt_swsysrst2; @@ -85,4 +88,5 @@ int pmif_spmi_init(struct pmif *arb); int spmi_config_master(void); void pmif_spmi_iocfg(void); +void pmif_spmi_config(struct pmif *arb, int mstid); #endif /* __SOC_MEDIATEK_PMIF_SPMI_H__ */ diff --git a/src/soc/mediatek/common/pmif_spmi.c b/src/soc/mediatek/common/pmif_spmi.c index afeeddf..5a359c7 100644 --- a/src/soc/mediatek/common/pmif_spmi.c +++ b/src/soc/mediatek/common/pmif_spmi.c @@ -8,9 +8,6 @@ #include <soc/pmif_sw.h> #include <soc/spmi.h> -#define PMIF_CMD_PER_3 (0x1 << PMIF_CMD_EXT_REG_LONG) -#define PMIF_CMD_PER_1_3 ((0x1 << PMIF_CMD_REG) | (0x1 << PMIF_CMD_EXT_REG_LONG)) - /* SPMI_MST, SPMI_SAMPL_CTRL */ DEFINE_BIT(SAMPL_CK_POL, 0) DEFINE_BITFIELD(SAMPL_CK_DLY, 3, 1) @@ -25,6 +22,11 @@ DEFINE_BITFIELD(SPM_SLEEP_REQ_SEL, 1, 0) DEFINE_BITFIELD(SCP_SLEEP_REQ_SEL, 10, 9) +__weak void pmif_spmi_config(struct pmif *arb, int mstid) +{ + /* Do nothing. */ +} + static int spmi_read_check(struct pmif *pmif_arb, int slvid) { u32 rdata = 0; @@ -127,23 +129,8 @@ static void pmif_spmi_enable(int mstid) { struct pmif *arb = get_pmif_controller(PMIF_SPMI, mstid); - u32 cmd_per; - /* clear all cmd permission for per channel */ - write32(&arb->mtk_pmif->inf_cmd_per_0, 0); - write32(&arb->mtk_pmif->inf_cmd_per_1, 0); - write32(&arb->mtk_pmif->inf_cmd_per_2, 0); - write32(&arb->mtk_pmif->inf_cmd_per_3, 0); - - /* enable if we need cmd 0~3 permission for per channel */ - cmd_per = PMIF_CMD_PER_3 << 28 | PMIF_CMD_PER_3 << 24 | - PMIF_CMD_PER_3 << 20 | PMIF_CMD_PER_3 << 16 | - PMIF_CMD_PER_3 << 8 | PMIF_CMD_PER_3 << 4 | - PMIF_CMD_PER_1_3 << 0; - write32(&arb->mtk_pmif->inf_cmd_per_0, cmd_per); - - cmd_per = PMIF_CMD_PER_3 << 4; - write32(&arb->mtk_pmif->inf_cmd_per_1, cmd_per); + pmif_spmi_config(arb, mstid); /* * set bytecnt max limitation. diff --git a/src/soc/mediatek/mt8188/pmif_spmi.c b/src/soc/mediatek/mt8188/pmif_spmi.c index 84e1cea..14c830f 100644 --- a/src/soc/mediatek/mt8188/pmif_spmi.c +++ b/src/soc/mediatek/mt8188/pmif_spmi.c @@ -61,6 +61,27 @@ return 0; } +void pmif_spmi_config(struct pmif *arb, int mstid) +{ + u32 cmd_per; + + /* Clear all cmd permission for per channel */ + write32(&arb->mtk_pmif->inf_cmd_per_0, 0); + write32(&arb->mtk_pmif->inf_cmd_per_1, 0); + write32(&arb->mtk_pmif->inf_cmd_per_2, 0); + write32(&arb->mtk_pmif->inf_cmd_per_3, 0); + + /* TODO: figure out correct setting for MT8188 */ + cmd_per = PMIF_CMD_PER_3 << 28 | PMIF_CMD_PER_3 << 24 | + PMIF_CMD_PER_3 << 20 | PMIF_CMD_PER_3 << 16 | + PMIF_CMD_PER_3 << 8 | PMIF_CMD_PER_3 << 4 | + PMIF_CMD_PER_1_3 << 0; + write32(&arb->mtk_pmif->inf_cmd_per_0, cmd_per); + + cmd_per = PMIF_CMD_PER_3 << 4; + write32(&arb->mtk_pmif->inf_cmd_per_1, cmd_per); +} + void pmif_spmi_iocfg(void) { SET32_BITFIELDS(&mtk_iocfg_lt->eh_cfg_clr, SPMI_SCL, 0x7, SPMI_SDA, 0x7); diff --git a/src/soc/mediatek/mt8192/pmif_spmi.c b/src/soc/mediatek/mt8192/pmif_spmi.c index 1862af5..d2155fa 100644 --- a/src/soc/mediatek/mt8192/pmif_spmi.c +++ b/src/soc/mediatek/mt8192/pmif_spmi.c @@ -56,6 +56,27 @@ return 0; } +void pmif_spmi_config(struct pmif *arb, int mstid) +{ + u32 cmd_per; + + /* Clear all cmd permission for per channel */ + write32(&arb->mtk_pmif->inf_cmd_per_0, 0); + write32(&arb->mtk_pmif->inf_cmd_per_1, 0); + write32(&arb->mtk_pmif->inf_cmd_per_2, 0); + write32(&arb->mtk_pmif->inf_cmd_per_3, 0); + + /* Enable if we need cmd 0~3 permission for per channel */ + cmd_per = PMIF_CMD_PER_3 << 28 | PMIF_CMD_PER_3 << 24 | + PMIF_CMD_PER_3 << 20 | PMIF_CMD_PER_3 << 16 | + PMIF_CMD_PER_3 << 8 | PMIF_CMD_PER_3 << 4 | + PMIF_CMD_PER_1_3 << 0; + write32(&arb->mtk_pmif->inf_cmd_per_0, cmd_per); + + cmd_per = PMIF_CMD_PER_3 << 4; + write32(&arb->mtk_pmif->inf_cmd_per_1, cmd_per); +} + void pmif_spmi_iocfg(void) { SET32_BITFIELDS(&mtk_iocfg_bm->drv_cfg2, SPMI_SCL, 0x2, SPMI_SDA, 0x2); diff --git a/src/soc/mediatek/mt8195/pmif_spmi.c b/src/soc/mediatek/mt8195/pmif_spmi.c index 6883dd2..ade44c5 100644 --- a/src/soc/mediatek/mt8195/pmif_spmi.c +++ b/src/soc/mediatek/mt8195/pmif_spmi.c @@ -66,6 +66,27 @@ return 0; } +void pmif_spmi_config(struct pmif *arb, int mstid) +{ + u32 cmd_per; + + /* Clear all cmd permission for per channel */ + write32(&arb->mtk_pmif->inf_cmd_per_0, 0); + write32(&arb->mtk_pmif->inf_cmd_per_1, 0); + write32(&arb->mtk_pmif->inf_cmd_per_2, 0); + write32(&arb->mtk_pmif->inf_cmd_per_3, 0); + + /* Enable if we need cmd 0~3 permission for per channel */ + cmd_per = PMIF_CMD_PER_3 << 28 | PMIF_CMD_PER_3 << 24 | + PMIF_CMD_PER_3 << 20 | PMIF_CMD_PER_3 << 16 | + PMIF_CMD_PER_3 << 8 | PMIF_CMD_PER_3 << 4 | + PMIF_CMD_PER_1_3 << 0; + write32(&arb->mtk_pmif->inf_cmd_per_0, cmd_per); + + cmd_per = PMIF_CMD_PER_3 << 4; + write32(&arb->mtk_pmif->inf_cmd_per_1, cmd_per); +} + void pmif_spmi_iocfg(void) { SET32_BITFIELDS(&mtk_iocfg_bm->eh_cfg_clr, SPMI_SCL, 0x7, SPMI_SDA, 0x7); -- To view, visit https://review.coreboot.org/c/coreboot/+/68619 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4cf508a0690995a7fe7b7316269d07cb7a799191 Gerrit-Change-Number: 68619 Gerrit-PatchSet: 5 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: soc/mediatek/mt8186: Add PMIF_SPMI_IOCFG_DEFAULT_SETTING Kconfig option
by Felix Held (Code Review) 21 Oct '22

21 Oct '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68578 ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/mediatek/mt8186: Add PMIF_SPMI_IOCFG_DEFAULT_SETTING Kconfig option ...................................................................... soc/mediatek/mt8186: Add PMIF_SPMI_IOCFG_DEFAULT_SETTING Kconfig option For MT8186, PMIF_SPMI mode is the hardware default setting, so we don't need to configure PMIF SPMI IO pins. Add a config to control that. BUG=b:249436110 TEST=build pass. BRANCH=corsola Signed-off-by: Bo-Chen Chen <rex-bc.chen(a)mediatek.com> Change-Id: I92b54e8379a5dec55ef95cbd72ce03abd3a4954b Reviewed-on: https://review.coreboot.org/c/coreboot/+/68578 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/common/Kconfig M src/soc/mediatek/common/pmif_spmi.c M src/soc/mediatek/mt8186/Kconfig 3 files changed, 31 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, but someone else must approve diff --git a/src/soc/mediatek/common/Kconfig b/src/soc/mediatek/common/Kconfig index ce9f883..62934da 100644 --- a/src/soc/mediatek/common/Kconfig +++ b/src/soc/mediatek/common/Kconfig @@ -70,4 +70,11 @@ When this option is enabled, the PMIC interface only supports PWRAP and PMIF_SPMI. +config PMIF_SPMI_IOCFG_DEFAULT_SETTING + bool + default n + help + For SoCs where IO pins default to PMIF_SPMI mode, enable this option + to skip software PMIF_SPMI IO pins configuration. + endif diff --git a/src/soc/mediatek/common/pmif_spmi.c b/src/soc/mediatek/common/pmif_spmi.c index 8ff7c1e..afeeddf 100644 --- a/src/soc/mediatek/common/pmif_spmi.c +++ b/src/soc/mediatek/common/pmif_spmi.c @@ -82,7 +82,8 @@ return -E_INVAL; } - pmif_spmi_iocfg(); + if (!CONFIG(PMIF_SPMI_IOCFG_DEFAULT_SETTING)) + pmif_spmi_iocfg(); spmi_config_master(); for (i = 0; i < spmi_dev_cnt; i++) diff --git a/src/soc/mediatek/mt8186/Kconfig b/src/soc/mediatek/mt8186/Kconfig index bac220e..e6cdb00 100644 --- a/src/soc/mediatek/mt8186/Kconfig +++ b/src/soc/mediatek/mt8186/Kconfig @@ -13,6 +13,7 @@ select USE_CBMEM_DRAM_INFO select FLASH_DUAL_IO_READ select PWRAP_WITH_PMIF_SPMI + select PMIF_SPMI_IOCFG_DEFAULT_SETTING if SOC_MEDIATEK_MT8186 -- To view, visit https://review.coreboot.org/c/coreboot/+/68578 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92b54e8379a5dec55ef95cbd72ce03abd3a4954b Gerrit-Change-Number: 68578 Gerrit-PatchSet: 5 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: soc/mediatek/mt8186: Add PWRAP_WITH_PMIF_SPMI Kconfig option
by Felix Held (Code Review) 21 Oct '22

21 Oct '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68577 ) Change subject: soc/mediatek/mt8186: Add PWRAP_WITH_PMIF_SPMI Kconfig option ...................................................................... soc/mediatek/mt8186: Add PWRAP_WITH_PMIF_SPMI Kconfig option On MT8186, PMIC interface supports PWRAP and PMIF_SPMI while other MediaTek SoCs support PMIF_SPMI and PMIF_SPI. BUG=b:249436110 TEST=build pass. BRANCH=corsola Signed-off-by: Bo-Chen Chen <rex-bc.chen(a)mediatek.com> Change-Id: I20efa6d84975d781972af9143c0c7e3a272653e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68577 Reviewed-by: Yidi Lin <yidilin(a)google.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/common/Kconfig M src/soc/mediatek/common/pmif.c M src/soc/mediatek/mt8186/Kconfig 3 files changed, 30 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, but someone else must approve diff --git a/src/soc/mediatek/common/Kconfig b/src/soc/mediatek/common/Kconfig index 119746b..ce9f883 100644 --- a/src/soc/mediatek/common/Kconfig +++ b/src/soc/mediatek/common/Kconfig @@ -63,4 +63,11 @@ When this option is enabled, the flash controller provides the ability to dual IO read mode. +config PWRAP_WITH_PMIF_SPMI + bool + default n + help + When this option is enabled, the PMIC interface only supports PWRAP + and PMIF_SPMI. + endif diff --git a/src/soc/mediatek/common/pmif.c b/src/soc/mediatek/common/pmif.c index a7ab4e5..a7076ee 100644 --- a/src/soc/mediatek/common/pmif.c +++ b/src/soc/mediatek/common/pmif.c @@ -297,7 +297,7 @@ ret = pmif_clk_init(); if (!ret) ret = pmif_spmi_init(get_pmif_controller(PMIF_SPMI, SPMI_MASTER_0)); - if (!ret) + if (!ret && !CONFIG(PWRAP_WITH_PMIF_SPMI)) ret = pmif_spi_init(get_pmif_controller(PMIF_SPI, 0)); return ret; diff --git a/src/soc/mediatek/mt8186/Kconfig b/src/soc/mediatek/mt8186/Kconfig index db5bed2..bac220e 100644 --- a/src/soc/mediatek/mt8186/Kconfig +++ b/src/soc/mediatek/mt8186/Kconfig @@ -12,6 +12,7 @@ select MEDIATEK_BLOB_FAST_INIT select USE_CBMEM_DRAM_INFO select FLASH_DUAL_IO_READ + select PWRAP_WITH_PMIF_SPMI if SOC_MEDIATEK_MT8186 -- To view, visit https://review.coreboot.org/c/coreboot/+/68577 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20efa6d84975d781972af9143c0c7e3a272653e0 Gerrit-Change-Number: 68577 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[master]: soc/mediatek/mt8186: Add support for reading CPU ID
by Felix Held (Code Review) 21 Oct '22

21 Oct '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68576 ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/mediatek/mt8186: Add support for reading CPU ID ...................................................................... soc/mediatek/mt8186: Add support for reading CPU ID MT8186 has two slightly different versions: MT8186G and MT8186T (turbo version). Add get_cpu_id() to identify different CPUs. BUG=b:249436110 TEST=cpu id is correct. BRANCH=corsola Signed-off-by: Bo-Chen Chen <rex-bc.chen(a)mediatek.com> Change-Id: I0612dd589e11853dbddc1d99526e9c9bf170acec Reviewed-on: https://review.coreboot.org/c/coreboot/+/68576 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- A src/soc/mediatek/common/cpu_id.c A src/soc/mediatek/common/include/soc/cpu_id.h M src/soc/mediatek/mt8186/Makefile.inc M src/soc/mediatek/mt8186/include/soc/efuse.h 4 files changed, 51 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, but someone else must approve diff --git a/src/soc/mediatek/common/cpu_id.c b/src/soc/mediatek/common/cpu_id.c new file mode 100644 index 0000000..e31adcd --- /dev/null +++ b/src/soc/mediatek/common/cpu_id.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/mmio.h> +#include <soc/cpu_id.h> +#include <soc/efuse.h> + +u32 get_cpu_id(void) +{ + u32 id = read32(&mtk_efuse->cpu_id_reg); + + printk(BIOS_INFO, "CPU: %#x\n", id); + + return id; +} diff --git a/src/soc/mediatek/common/include/soc/cpu_id.h b/src/soc/mediatek/common/include/soc/cpu_id.h new file mode 100644 index 0000000..9453a15 --- /dev/null +++ b/src/soc/mediatek/common/include/soc/cpu_id.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_COMMON_CPU_ID_H +#define SOC_MEDIATEK_COMMON_CPU_ID_H + +#define MTK_CPU_ID_MT8186G 0x81861001 +#define MTK_CPU_ID_MT8186T 0x81862001 + +u32 get_cpu_id(void); + +#endif /* SOC_MEDIATEK_COMMON_CPU_ID_H */ diff --git a/src/soc/mediatek/mt8186/Makefile.inc b/src/soc/mediatek/mt8186/Makefile.inc index cd20777..c8dbbc9 100644 --- a/src/soc/mediatek/mt8186/Makefile.inc +++ b/src/soc/mediatek/mt8186/Makefile.inc @@ -1,6 +1,7 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8186),y) # for bootblock, verstage, romstage, ramstage +all-y += ../common/cpu_id.c all-y += ../common/flash_controller.c all-y += ../common/gpio.c ../common/gpio_op.c gpio.c all-y += ../common/i2c.c i2c.c diff --git a/src/soc/mediatek/mt8186/include/soc/efuse.h b/src/soc/mediatek/mt8186/include/soc/efuse.h index fe3dfff..3804b46 100644 --- a/src/soc/mediatek/mt8186/include/soc/efuse.h +++ b/src/soc/mediatek/mt8186/include/soc/efuse.h @@ -9,9 +9,12 @@ struct efuse_regs { uint32_t reserved[130]; uint32_t adc_cali_reg; + uint32_t reserved1[357]; + uint32_t cpu_id_reg; }; check_member(efuse_regs, adc_cali_reg, 0x208); +check_member(efuse_regs, cpu_id_reg, 0x7a0); static struct efuse_regs *const mtk_efuse = (void *)EFUSEC_BASE; #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/68576 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0612dd589e11853dbddc1d99526e9c9bf170acec Gerrit-Change-Number: 68576 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: mb/lenovo/s230u/mainboard.c: Replace comma with semicolon
by Felix Held (Code Review) 21 Oct '22

21 Oct '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67970 ) Change subject: mb/lenovo/s230u/mainboard.c: Replace comma with semicolon ...................................................................... mb/lenovo/s230u/mainboard.c: Replace comma with semicolon Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Change-Id: I9e8ad533e939553a93e76f1dbb37fc98b53f06d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67970 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/lenovo/s230u/mainboard.c 1 file changed, 14 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/lenovo/s230u/mainboard.c b/src/mainboard/lenovo/s230u/mainboard.c index 7f2c7fd..b5e3b87 100644 --- a/src/mainboard/lenovo/s230u/mainboard.c +++ b/src/mainboard/lenovo/s230u/mainboard.c @@ -51,7 +51,7 @@ static void mainboard_enable(struct device *dev) { - dev->ops->get_smbios_strings = mainboard_smbios_strings, + dev->ops->get_smbios_strings = mainboard_smbios_strings; install_intel_vga_int15_handler( GMA_INT15_ACTIVE_LFP_INT_LVDS, -- To view, visit https://review.coreboot.org/c/coreboot/+/67970 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e8ad533e939553a93e76f1dbb37fc98b53f06d6 Gerrit-Change-Number: 67970 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: arm64/armv8: Use 'enum cb_err'
by Felix Held (Code Review) 21 Oct '22

21 Oct '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68370 ) Change subject: arm64/armv8: Use 'enum cb_err' ...................................................................... arm64/armv8: Use 'enum cb_err' Change-Id: Ic4ce44865544c94c39e8582780a7eca7876f5c38 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68370 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/arch/arm64/armv8/exception.c M src/arch/arm64/include/armv8/arch/exception.h 2 files changed, 23 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/src/arch/arm64/armv8/exception.c b/src/arch/arm64/armv8/exception.c index f3a0755..80b619d 100644 --- a/src/arch/arm64/armv8/exception.c +++ b/src/arch/arm64/armv8/exception.c @@ -65,25 +65,25 @@ static struct exception_handler *handlers[NUM_EXC_VIDS]; -int exception_handler_register(uint64_t vid, struct exception_handler *h) +enum cb_err exception_handler_register(uint64_t vid, struct exception_handler *h) { if (vid >= NUM_EXC_VIDS) - return -1; + return CB_ERR; /* Just place at head of queue. */ h->next = handlers[vid]; store_release(&handlers[vid], h); - return 0; + return CB_SUCCESS; } -int exception_handler_unregister(uint64_t vid, struct exception_handler *h) +enum cb_err exception_handler_unregister(uint64_t vid, struct exception_handler *h) { struct exception_handler *cur; struct exception_handler **prev; if (vid >= NUM_EXC_VIDS) - return -1; + return CB_ERR; prev = &handlers[vid]; @@ -92,11 +92,11 @@ continue; /* Update previous pointer. */ store_release(prev, cur->next); - return 0; + return CB_SUCCESS; } /* Not found */ - return -1; + return CB_ERR; } static void print_exception_info(struct exc_state *state, uint64_t idx) diff --git a/src/arch/arm64/include/armv8/arch/exception.h b/src/arch/arm64/include/armv8/arch/exception.h index 72ed772..2c5b7f9 100644 --- a/src/arch/arm64/include/armv8/arch/exception.h +++ b/src/arch/arm64/include/armv8/arch/exception.h @@ -4,6 +4,7 @@ #define _ARCH_EXCEPTION_H #include <arch/transition.h> +#include <types.h> /* Initialize the exception handling on the current CPU. */ void exception_init(void); @@ -31,12 +32,12 @@ * Register a handler provided with the associated vector id. Returns 0 on * success, < 0 on error. Note that registration is not thread/interrupt safe. */ -int exception_handler_register(uint64_t vid, struct exception_handler *h); +enum cb_err exception_handler_register(uint64_t vid, struct exception_handler *h); /* * Unregister a handler from the vector id. Return 0 on success, < 0 on error. * Note that the unregistration is not thread/interrupt safe. */ -int exception_handler_unregister(uint64_t vid, struct exception_handler *h); +enum cb_err exception_handler_unregister(uint64_t vid, struct exception_handler *h); #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/68370 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4ce44865544c94c39e8582780a7eca7876f5c38 Gerrit-Change-Number: 68370 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: soc/amd/morgana/aoac: Remove to-do after review
by Felix Held (Code Review) 21 Oct '22

21 Oct '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68580 ) Change subject: soc/amd/morgana/aoac: Remove to-do after review ...................................................................... soc/amd/morgana/aoac: Remove to-do after review Reviewed files and values match morgana ppr #57396, rev 1.52 Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Change-Id: I6772b21110f74a77eef285da3e1f313ec6326cc8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68580 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/morgana/aoac.c M src/soc/amd/morgana/include/soc/aoac_defs.h 2 files changed, 15 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/morgana/aoac.c b/src/soc/amd/morgana/aoac.c index d4f96df..ab52544 100644 --- a/src/soc/amd/morgana/aoac.c +++ b/src/soc/amd/morgana/aoac.c @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* TODO: Update for Morgana */ - #include <stdint.h> #include <amdblocks/acpimmio.h> #include <amdblocks/aoac.h> diff --git a/src/soc/amd/morgana/include/soc/aoac_defs.h b/src/soc/amd/morgana/include/soc/aoac_defs.h index c52f502..a93f06d 100644 --- a/src/soc/amd/morgana/include/soc/aoac_defs.h +++ b/src/soc/amd/morgana/include/soc/aoac_defs.h @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* TODO: Update for Morgana */ - #ifndef AMD_MORGANA_AOAC_DEFS_H #define AMD_MORGANA_AOAC_DEFS_H -- To view, visit https://review.coreboot.org/c/coreboot/+/68580 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6772b21110f74a77eef285da3e1f313ec6326cc8 Gerrit-Change-Number: 68580 Gerrit-PatchSet: 2 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2022