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Change subject: soc/intel/xeon_sp: Add functions to store/restore uart state in smm
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Patch Set 4: Code-Review+2
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Change subject: src/drivers/uart: Add definition of FIFO enabled in Interrupt Identification Register
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Patch Set 2: Code-Review+2
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Change subject: acpi/Kconfig: Remove unused ACPI_EINJ config option
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Patch Set 1:
(1 comment)
Patchset:
PS1:
EINJ is an important feature which allows hardware error injection. It is not used in the upstream code base because there is IP sensitive code involved in the flow. We are brainstorming on how to get around that.
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Change subject: commonlib/fsp_relocate: Fix Coverity Issues
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Patch Set 1:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68637/comment/0f67df0b_957cf194
PS1, Line 7: commonlib/fsp_relocate: Fix Coverity Issues
Pls. refer to these existing coverity related commits:
$ git log --oneline | grep -i coverity
94e4961a01 acpi: Fix Coverity Scan report
7777e1c30b ec/google/chromeec: Fix Coverity Scan error (BAD_SHIFT)
423adfb0d3 x86/acpi: Fix Coverity issue CID 1399153
b431833c12 Docs/project_ideas: Add coverity scan cleanup project
c75f2d8119 arch/x86/acpi_bert_storage.c: Fix coverity error CID 1395706
013ebbfa58 soc/intel/cannonlake: Fix Coverity Scan report
4461613119 cavium/bdk: Fix coverity and remove hardcoded DRAM speed
ded0c77d48 Coverity: Fix CID1393976
f4d81e0385 Coverity: Fix CID1393978
679d624fae Coverity: Fix CID1393979
feefbd7127 soc/intel/cannonlake: Fix Coverity scan error
f797a1ac6a riscv: Suppress invalid coverity errors
https://review.coreboot.org/c/coreboot/+/68637/comment/7505b178_657a5773
PS1, Line 9: Recently committed change 1df1cf9 resulted in some Coverity
Use [CB: gerrid ID] as the hyper-link.
https://review.coreboot.org/c/coreboot/+/68637/comment/85e98269_f3a97a5c
PS1, Line 14: This code is tested with FSP version 33A for DeltaLake boot
FSP --> Intel CooperLake-SP FSP
33A, needs to be the full version number.
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Change subject: soc/intel: Add node_num to dimm_info struct + adjust dimm_info_fill
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Patch Set 4:
(1 comment)
File src/include/memory_info.h:
https://review.coreboot.org/c/coreboot/+/68525/comment/9ecb7916_379fffb1
PS4, Line 96: * Node-ID / Memory-Controller-ID
Is there any reason naming it Node-ID instead of Controller-ID? Initially I thought it meant socket ID.
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Change subject: mb/prodrive/atlas: Disable S3
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Patch Set 2:
(1 comment)
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https://review.coreboot.org/c/coreboot/+/68591/comment/c43e4692_c64ea1d9
PS2, Line 9: currenlty
typo: currently
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Change subject: nb/intel/i945/raminit: Use 'size_t' for banksize[]
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Patch Set 7: Code-Review+2
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Change subject: scripts/update_submodules: Fix "bad revision" error
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Patch Set 4: Code-Review+1
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Change subject: mb/siemens/mc_ehl1: Disable L1 prefetcher
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Patch Set 2: Code-Review+2
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Change subject: soc/intel/eklhartlake: Provide an option to disable the L1 prefetcher
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Patch Set 2: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68667/comment/80192a62_92eb9f1a
PS2, Line 11: This will in the end
How about:
In the end, this will ...
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