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Change subject: mb/google/guybrush/var/nipperkin: update USB 2.0 controller Lane Parameter
......................................................................
mb/google/guybrush/var/nipperkin: update USB 2.0 controller Lane Parameter
Enhance USB 2.0 SI by increasing the level of "HS DC Voltage Level"
and "Disconnect Threshold Adjustment" per port:
port#0: COMPDISTUNE0: 0x1->0x5 / TXVREFTUNE0: 0x3->0x9
port#1: COMPDISTUNE0: 0x1->0x5 / TXVREFTUNE0: 0x3->0x9
port#4: COMPDISTUNE0: 0x1->0x6 / TXVREFTUNE0: 0x3->0xE
port#5: COMPDISTUNE0: 0x1->0x5 / TXVREFTUNE0: 0x3->0x9
BUG=b:203049656
BRANCH=guybrush
TEST=1. emerge-guybrush coreboot chromeos-bootimage
2. pass USB eye diagram verification
Change-Id: If5a6563e93bfa6beb529a5593fcc9124ce62d77f
Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com>
---
M src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb
1 file changed, 133 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/60089/3
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Change subject: mb/google/guybrush/var/nipperkin: update USB 2.0 controller Lane Parameter
......................................................................
Patch Set 2:
This change is ready for review.
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Change subject: mb/google/brya/var/vell: Add AMP driver setting
......................................................................
Patch Set 7:
(2 comments)
Patchset:
PS7:
> I will review in more details tomorrow.
>
> But here is my quick feedback.
>
> I'm recommending to split this CL into atleast 3 CLs as below:
>
> 1. Add I2C driver for CS35L53 support.
Please consider to check CB:52395 commit msg and while splitting this CL.
> 2. Configure GPIO for vell variant.
> 2. Let Brya Kconfig.name to select this for vell variant and required override dt changes.
File src/drivers/i2c/cs35l53/cs35l53.c:
https://review.coreboot.org/c/coreboot/+/60331/comment/6a44514c_afba9391
PS7, Line 2:
> one interesting observation that I have post reviewing this Cirrus Logic 35L53 and Cirrus Logic CS42 […]
@Tim/Nick, what do you think ?
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Change subject: drvs/intel/gma/acpi: Add methods to use MBOX3
......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS7:
> The line makes 0x2000 bytes (8KiB) of RAM accessible to the ASL code around […]
Issue https://ticket.coreboot.org/issues/327 was created for this.
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Change subject: mb/google/brya/var/vell: Add AMP driver setting
......................................................................
Patch Set 7:
(11 comments)
File src/drivers/i2c/cs35l53/chip.h:
https://review.coreboot.org/c/coreboot/+/60331/comment/f3508d55_61a1ed6d
PS7, Line 2:
Can you please help me to get the product datasheet? I have tried getting from product site but its asking for purchasing details. Possible to create a partner bug and upload the doc?
https://www.cirrus.com/products/cs35l45/https://review.coreboot.org/c/coreboot/+/60331/comment/a6e1797d_772d4268
PS7, Line 36:
nit: please remove extra space?
https://review.coreboot.org/c/coreboot/+/60331/comment/5af78710_debc3e2d
PS7, Line 41: /* ACPI Dev
nit: move this to line above to maintain the parity with other comments in this file ?
File src/drivers/i2c/cs35l53/cs35l53.c:
https://review.coreboot.org/c/coreboot/+/60331/comment/714dcf54_326f5fde
PS7, Line 2:
one interesting observation that I have post reviewing this Cirrus Logic 35L53 and Cirrus Logic CS42L42 (existing code in coreboot) is that, except the _DSD implementation, rest of the code is exactly same. One just need to pass the configuration options like _HID.
https://review.coreboot.org/c/coreboot/+/60331/comment/6053974a_154e99ca
PS7, Line 24: .speed = config->bus_speed ? : I2C_SPEED_FAST,
> shouldn't this be […]
Mostly its coming from here
https://github.com/coreboot/coreboot/blob/master/src/drivers/i2c/cs42l42/cs…
When nothing appears between ?:, then the value of the comparison is used in the true case.
Therefore, the expression
x ? : y
has the value of x if that is nonzero; otherwise, the value of y.
This example is perfectly equivalent to
x ? x : y
https://review.coreboot.org/c/coreboot/+/60331/comment/ce932540_8f047491
PS7, Line 57: AAD
> what is AAD?
Advanced Accessory Detection (AAD)
This is what I found while Googling on kernel code:
The Advanced Accessory Detection (AAD) will detect a jack insertion/removal, detect the polarity of the jack (CTIA/OMTP), and will support the detection of impedance based buttons in parallel with the connected accessory microphone.
https://review.coreboot.org/c/coreboot/+/60331/comment/5ac3bad8_fe6a3cce
PS7, Line 70: if ((config->boost_peak_milliamp > 4500) ||
: (config->boost_peak_milliamp < 1600) ||
: (config->boost_peak_milliamp % 50)){
please reflow it till 96 line?
https://review.coreboot.org/c/coreboot/+/60331/comment/3ca079f2_f480d67b
PS7, Line 82: acpi_dp_add_integer(dsd, "cirrus,gpio1-polarity-invert", config->gpio1_polarity_invert ? 1 : 0);
> line over 96 characters
Please fix.
https://review.coreboot.org/c/coreboot/+/60331/comment/6c7c6fff_4b6bf62b
PS7, Line 85: acpi_dp_add_integer(dsd, "cirrus,gpio2-polarity-invert", config->gpio2_polarity_invert ? 1 : 0);
> line over 96 characters
Please fix.
https://review.coreboot.org/c/coreboot/+/60331/comment/8fa5829f_7d94aefd
PS7, Line 86: acpi_dp_add_integer(dsd, "cirrus,gpio2-output-enable", config->gpio2_output_enable ? 1 : 0);
> line over 96 characters
Please fix.
https://review.coreboot.org/c/coreboot/+/60331/comment/6297e707_dfce7847
PS7, Line 102: // return CS35L53_ACPI_NAME;
while not just return the ACPI name. if you are not planning to use CS35L53_ACPI_NAME then there is no need for this macro?
return CS35L53_ACPI_NAME;
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Change subject: mb/google/herobrine: Initialize SPI FW for EC and TPM
......................................................................
Patch Set 95:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/50581/comment/e8e584ea_5cc96821
PS71, Line 10: Load QUP FW in respective Serial Engines.
> Paul, this is an unfinished platform port. […]
Understood. Then the commit message and/or TEST= line should make that clear.
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Change subject: IASL: Ignore IASL's "Missing dependency" warning
......................................................................
Patch Set 6:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59880/comment/4a81d12d_ab5806aa
PS1, Line 16:
> No, but maybe we can have it from here: https://qa.coreboot. […]
It’d be nice to only disable the warning for boards having the problem.
Patchset:
PS5:
> I'm not sure if my English is clear 😊 […]
Indeed it’d be great to only silence the warning for known problematic boards.
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Change subject: mb/google/brya/var/gimble: Update Slow Slew Rate
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60277/comment/5d8431e1_d83fa654
PS2, Line 9: - Set slow slew rate VCCIA and VCCGT to 8
Please give a motivation or reasoning for the change next time.
https://review.coreboot.org/c/coreboot/+/60277/comment/47fd6e5e_26701424
PS2, Line 12: USE=
Is USE= a new tag?
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Change subject: mb/google/brya/var/gimble4es: Configure Acoustic noise mitigation
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59949/comment/9a8e3e82_735753a9
PS1, Line 10: - Set slow slew rate VCCIA and VCCGT to 16
The referenced change-set actually has:
> - Set slow slew rate VCCIA and VCCGT to 16
Please, make it easy for non-Chromium folks to understand and review changes. There are plenty of examples, where some time (months/years) later it is impossible to figure out the reason for a change.
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Comment-In-Reply-To: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com>
Gerrit-MessageType: comment
Attention is currently required from: Felix Singer, Tim Wawrzynczak, Casper Chang.
Hello Felix Singer, build bot (Jenkins), Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/60104
to look at the new patch set (#25).
Change subject: mb/google/brya/var/primus: Fix some GPIO programming
......................................................................
mb/google/brya/var/primus: Fix some GPIO programming
During the initial review, a few unused GPIOs that were inherited
from the baseboard were missed, so this CL programs them as PAD_NC.
GPP_B2 => non-use
GPP_B15 => non-use (for FPR)
GPP_D3 => non-use (Test point)
GPP_E21 => non-use (for LCLW Detect)
BUG=b:211721639
TEST= USE="project_primus" emerge-brya coreboot and verify it builds without error.
Signed-off-by: Ariel_Fang <ariel_fang(a)wistron.corp-partner.google.com>
Change-Id: I4e269bc6fb6eda7b2de57e1a9c900864d3e86e98
---
M src/mainboard/google/brya/variants/primus/gpio.c
M src/mainboard/google/brya/variants/primus4es/gpio.c
2 files changed, 17 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/60104/25
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I4e269bc6fb6eda7b2de57e1a9c900864d3e86e98
Gerrit-Change-Number: 60104
Gerrit-PatchSet: 25
Gerrit-Owner: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com>
Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
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Gerrit-MessageType: newpatchset