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Change subject: cpu/x86/lapic: Fix choice X2APIC_ONLY
......................................................................
cpu/x86/lapic: Fix choice X2APIC_ONLY
When sending self an IPI, some instructions may be processed
before IPI is serviced. Spend some time doing nothing, to
avoid entering a printk() and acquiring console_lock and
dead-locking.
Change-Id: I78070ae91e78c11c3e3aa225e5673d4667d6f7bb
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/include/cpu/x86/lapic.h
1 file changed, 8 insertions(+), 0 deletions(-)
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Change subject: libpayload: Implement new CBFS access API
......................................................................
libpayload: Implement new CBFS access API
This commit adds new CBFS API, which is based on the one available in
the main coreboot source tree. Libpayload implementation supports RO/RW
file lookups and file contents verification.
Change-Id: I00da0658dbac0cddf92ad55611def947932d23c7
Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com>
---
M payloads/libpayload/Kconfig
M payloads/libpayload/Makefile.inc
M payloads/libpayload/include/cbfs.h
M payloads/libpayload/include/cbfs_core.h
A payloads/libpayload/include/cbfs_glue.h
A payloads/libpayload/include/cbfs_legacy.h
A payloads/libpayload/libcbfs/Kconfig
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M payloads/libpayload/libcbfs/cbfs.c
M payloads/libpayload/libcbfs/cbfs_core.c
A payloads/libpayload/libcbfs/cbfs_legacy.c
M payloads/libpayload/tests/Makefile.inc
A payloads/libpayload/tests/include/mocks/cbfs_util.h
A payloads/libpayload/tests/libcbfs/Makefile.inc
A payloads/libpayload/tests/libcbfs/cbfs-lookup-test.c
A payloads/libpayload/tests/libcbfs/cbfs-lookup.test.c
A payloads/libpayload/tests/libcbfs/cbfs-verification-test.c
A payloads/libpayload/tests/mocks/cbfs_file_mock.c
A payloads/libpayload/tests/mocks/die.c
19 files changed, 1,813 insertions(+), 437 deletions(-)
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Change subject: libpayload: Implement new CBFS access API
......................................................................
libpayload: Implement new CBFS access API
Change-Id: I00da0658dbac0cddf92ad55611def947932d23c7
Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com>
---
M payloads/libpayload/Kconfig
M payloads/libpayload/Makefile.inc
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M payloads/libpayload/include/cbfs_core.h
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A payloads/libpayload/tests/libcbfs/cbfs-verification-test.c
A payloads/libpayload/tests/mocks/cbfs_file_mock.c
A payloads/libpayload/tests/mocks/die.c
19 files changed, 1,814 insertions(+), 432 deletions(-)
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Change subject: libpayload: Enable vboot integration
......................................................................
libpayload: Enable vboot integration
This patch introduces building and linking of 3rdparty/vboot with
libpayload. VBoot can be enabled by setting CONFIG_LP_VBOOT_LIB.
Moreover it can be configured to use either TPM or TPM 2.0 mode,
and whether to use SHA256 processor extension instructions on x86.
Change-Id: I2d9d766a461edaa0081041c020ecf580fd2ca64e
Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com>
---
M payloads/libpayload/Kconfig
M payloads/libpayload/Makefile
M payloads/libpayload/Makefile.inc
A payloads/libpayload/vboot/Kconfig
A payloads/libpayload/vboot/Makefile.inc
5 files changed, 85 insertions(+), 4 deletions(-)
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Change subject: arch/x86/spinlock.h: Support systems with >128 cores
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60539/comment/79d6d426_fe2e7656
PS1, Line 12: spinlock acquiring and releasing.
Could you add some TEST: line, and the point of failure (MP init, SMM relocation?) you experienced the problem with.
Patchset:
PS1:
Can you add
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Change subject: mb/google/brya/var/taeko: Run-time probe for NVMe SSD and MMC
......................................................................
Patch Set 13:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60341/comment/3e42d086_7548d322
PS11, Line 14: TEST=Test on takeo trace in FSP log can found setting correct
> We verified that PCIE Port 9 is enabled in fsp log.
To complement, we use root port 9 for emmc and cpu pcie rp 1 for ssd. We can see the correct root ports are enabled in FSP log depending on the current cbi.
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Joey Peng has uploaded a new patch set (#13) to the change originally created by Kevin Chang. ( https://review.coreboot.org/c/coreboot/+/60341 )
Change subject: mb/google/brya/var/taeko: Run-time probe for NVMe SSD and MMC
......................................................................
mb/google/brya/var/taeko: Run-time probe for NVMe SSD and MMC
Taeko will use two PCIE port signals with one slot, one CLK and one
CLKREQ. In order to accommodate this, probe statements are added to the
devicetree. This only affects NVME SSD and EMMC.
BUG=b:211914322
TEST=Test on takeo trace in FSP log can find the correct root ports have
been set depending on CBI.
Cq-Depend: chromium:3358662
Signed-off-by: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com>
Change-Id: I4486f23ea02374c84a9b1ce04f568d78aeabd573
---
M src/mainboard/google/brya/variants/taeko/overridetree.cb
1 file changed, 12 insertions(+), 2 deletions(-)
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Change subject: mb/google/brya/var/taeko: Run-time probe for NVMe SSD and MMC
......................................................................
Patch Set 12:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60341/comment/0b5854f7_4ab27072
PS11, Line 14: TEST=Test on takeo trace in FSP log can found setting correct
> Updated in commit message.
We verified that PCIE Port 9 is enabled in fsp log.
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Change subject: mb/google/brya/var/taeko: Run-time probe for NVMe SSD and MMC
......................................................................
Patch Set 12:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60341/comment/c7cd6e35_91984f3b
PS11, Line 7: Add judgement for PCIE signal switch
> Maybe (if correct): […]
Done
https://review.coreboot.org/c/coreboot/+/60341/comment/5a3c1b24_d9ec9db2
PS11, Line 12:
> Please elaborate. […]
Yes, it only affects SSD and EMMC. Added in commit message.
https://review.coreboot.org/c/coreboot/+/60341/comment/494fb865_77103d91
PS11, Line 14: TEST=Test on takeo trace in FSP log can found setting correct
> What does the trace say?
Updated in commit message.
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