coreboot-gerrit January 2022

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Change in coreboot[master]: src/drivers: Remove unused <string.h>
by HAOUAS Elyes (Code Review) 03 Jan '22

03 Jan '22

Attention is currently required from: Patrick Rudolph. Hello build bot (Jenkins), Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60552 to look at the new patch set (#5). Change subject: src/drivers: Remove unused <string.h> ...................................................................... src/drivers: Remove unused <string.h> Found using following command: diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy(\|memmove(\|memset(\|memcmp(\|memchr(\|strdup(\|strconcat(\|strnlen(\|strlen(\|strchr(\|strncpy(\|strcpy(\|strcmp(\|strncmp(\|strspn(\|strcspn(\|strstr(\|strtok_r(\|strtok(\|atol(\|strrchr(\|skip_atoi(\|vsnprintf(\|snprintf(' -- src/) Change-Id: I2a6c5b67af1d2544159e92d4b8c06cc1f5504bd2 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/acpi/thermal_zone/thermal_zone.c M src/drivers/amd/i2s_machine_dev/i2s_machine_dev.c M src/drivers/generic/gpio_keys/gpio_keys.c M src/drivers/i2c/generic/generic.c M src/drivers/i2c/gpiomux/bus/bus.c M src/drivers/i2c/gpiomux/mux/mux.c M src/drivers/i2c/sx9310/sx9310.c M src/drivers/i2c/sx9324/sx9324.c M src/drivers/intel/gma/acpi.c M src/drivers/intel/usb4/retimer/retimer.c M src/drivers/spi/acpi/acpi.c M src/drivers/uart/acpi/acpi.c M src/drivers/wifi/generic/smbios.c 13 files changed, 9 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/60552/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/60552 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a6c5b67af1d2544159e92d4b8c06cc1f5504bd2 Gerrit-Change-Number: 60552 Gerrit-PatchSet: 5 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel: Remove unused <string.h>
by HAOUAS Elyes (Code Review) 03 Jan '22

03 Jan '22

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60553 ) Change subject: soc/intel: Remove unused <string.h> ...................................................................... Patch Set 4: (1 comment) Patchset: PS3: > Hmm, that is a lot of files to verify at one time that shouldn't have string.h included... easy to find using: diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy(\|memmove(\|memset(\|memcmp(\|memchr(\|strdup(\|strconcat(\|strnlen(\|strlen(\|strchr(\|strncpy(\|strcpy(\|strcmp(\|strncmp(\|strspn(\|strcspn(\|strstr(\|strtok_r(\|strtok(\|atol(\|strrchr(\|skip_atoi(\|vsnprintf(\|snprintf(' -- src/) -- To view, visit https://review.coreboot.org/c/coreboot/+/60553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae90ff482f534d8de2a519619c20a019d054e700 Gerrit-Change-Number: 60553 Gerrit-PatchSet: 4 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 03 Jan 2022 15:20:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: Remove unused <string.h>
by HAOUAS Elyes (Code Review) 03 Jan '22

03 Jan '22

Attention is currently required from: Patrick Rudolph, HAOUAS Elyes. Hello build bot (Jenkins), Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60553 to look at the new patch set (#4). Change subject: soc/intel: Remove unused <string.h> ...................................................................... soc/intel: Remove unused <string.h> Found using following command: diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy(\|memmove(\|memset(\|memcmp(\|memchr(\|strdup(\|strconcat(\|strnlen(\|strlen(\|strchr(\|strncpy(\|strcpy(\|strcmp(\|strncmp(\|strspn(\|strcspn(\|strstr(\|strtok_r(\|strtok(\|atol(\|strrchr(\|skip_atoi(\|vsnprintf(\|snprintf(' -- src/) Change-Id: Iae90ff482f534d8de2a519619c20a019d054e700 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/alderlake/acpi.c M src/soc/intel/cannonlake/acpi.c M src/soc/intel/common/block/irq/irq.c M src/soc/intel/elkhartlake/acpi.c M src/soc/intel/elkhartlake/fsp_params.c M src/soc/intel/elkhartlake/romstage/fsp_params.c M src/soc/intel/icelake/acpi.c M src/soc/intel/jasperlake/acpi.c M src/soc/intel/jasperlake/romstage/fsp_params.c M src/soc/intel/tigerlake/acpi.c 10 files changed, 0 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/60553/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/60553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae90ff482f534d8de2a519619c20a019d054e700 Gerrit-Change-Number: 60553 Gerrit-PatchSet: 4 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/acpi/pep: Use correct size_t length modifier
by Tim Wawrzynczak (Code Review) 03 Jan '22

03 Jan '22

Attention is currently required from: Paul Menzel, Angel Pons, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59057 ) Change subject: soc/intel/common/acpi/pep: Use correct size_t length modifier ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59057 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27bce0a6c62b1c1ebbca732761de2f59b042a5d4 Gerrit-Change-Number: 59057 Gerrit-PatchSet: 2 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 03 Jan 2022 15:15:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: irq: Use correct size_t length modifier
by Tim Wawrzynczak (Code Review) 03 Jan '22

03 Jan '22

Attention is currently required from: Paul Menzel, Angel Pons, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59056 ) Change subject: soc/intel/common: irq: Use correct size_t length modifier ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59056 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I09f4a8d22a2964471344f5dcf971dfa801555f4a Gerrit-Change-Number: 59056 Gerrit-PatchSet: 2 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 03 Jan 2022 15:14:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/gimble: Update Slow Slew Rate
by Tim Wawrzynczak (Code Review) 03 Jan '22

03 Jan '22

Attention is currently required from: Mark Hsieh. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60277 ) Change subject: mb/google/brya/var/gimble: Update Slow Slew Rate ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/60277/comment/d4b90621_05fd136c PS2, Line 9: - Set slow slew rate VCCIA and VCCGT to 8 > Please give a motivation or reasoning for the change next time. Sorry, To match gimble4es https://review.coreboot.org/c/coreboot/+/60277/comment/0f46840d_2b88c25e PS2, Line 12: USE= > Is USE= a new tag? No, it is setting a portage `USE` flag, i.e. https://wiki.gentoo.org/wiki/USE_flag the tag is still TEST= -- To view, visit https://review.coreboot.org/c/coreboot/+/60277 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e36c29e82af631cd650d46b67f031d275c97711 Gerrit-Change-Number: 60277 Gerrit-PatchSet: 2 Gerrit-Owner: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-Attention: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Comment-Date: Mon, 03 Jan 2022 15:13:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86/acpi: Replace Add(a,b,c) with ASL 2.0 syntax
by Tim Wawrzynczak (Code Review) 03 Jan '22

03 Jan '22

Attention is currently required from: Felix Singer, Lance Zhao, Nico Huber. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60645 ) Change subject: arch/x86/acpi: Replace Add(a,b,c) with ASL 2.0 syntax ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > In the past, we had patches that covered all changes in a file that > didn't change the AML and a separate one for things that did change > AML. It's not always wrong when it changes, for instance there are > multiple ways to store the result, Store() vs. last argument to an > op. IIRC, with the old syntax the compiler translated things literally > while with the new syntax it tries to optimize that. Just an example, > the compiler might behave differently by now. That is a good point, I am not sure how much "optimization" IASL applies to the resulting AML. > > 2) medium Per-Method or per-Device changes > > This sounds reasonable. I guess I wouldn't mind if the surrounding > code would look consistent. For the piecemeal approach to ASL 1.0 -> 2.0 syntax updates, this has the advantage of keeping at least some consistency > > 3) Small, per-operand changes which are nearly trivial to review > > Well, I don't doubt that there are trivial changes. But it doesn't > seem trivial to decide which are trivial and which are not. The > spec says the new ops act like their C equivalents but it already > contradicts itself with the precedence rules. And I have doubts > that things like &&, || really do the same that we are used to. That is a very good point, compound expressions may not have exactly the same AML output, even if the result is the same (or not, I don't know offhand if && and || are lazily evaluated like C...) > There may be more such subtleties. Over all, it seems the ASL 2.0 > ops do what the ASL designers *believed* their C equivalents would > do :D > OTOH, I wouldn't mind keeping per-op changes. Even if we only > compare the AML after a dozen changes, the commit message can > say so and we'd submit them all at once? The tricky part seems > to be to find which hunks result in AML changes and which don't. > How the patches that don't result in AML changes are organized > doesn't seem to matter that much. I would hope something like ``` ... Store(Local0, Local1) ``` vs. translates literally into ``` Local1 = Local0 ``` and both have the exact same AML representation. I guess the compound expressions (or things like lazy evaluations after &&) may prove to be the trickiest parts to update confidently without testing. Reminds me, I should go through and start updating at least the chrome EC ASL code wholesale to 2.0 syntax, that is easy enough for me to test. -- To view, visit https://review.coreboot.org/c/coreboot/+/60645 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id2a0b13522761e7113d1dc5b78d0dfd19a6cfd94 Gerrit-Change-Number: 60645 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Lance Zhao Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Mon, 03 Jan 2022 15:09:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp: Map FSP debug level to coreboot console level
by Nico Huber (Code Review) 03 Jan '22

03 Jan '22

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60471 ) Change subject: drivers/intel/fsp: Map FSP debug level to coreboot console level ...................................................................... Patch Set 7: (1 comment) Patchset: PS7: Meh, Gerrit showed the relation chain out-of-order but it's fine now I hope :) -- To view, visit https://review.coreboot.org/c/coreboot/+/60471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I398d576fad68a0d0fc931c175bbc04fcbc2e54ec Gerrit-Change-Number: 60471 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 03 Jan 2022 15:08:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp: Map FSP debug level to coreboot console level
by Nico Huber (Code Review) 03 Jan '22

03 Jan '22

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60471 ) Change subject: drivers/intel/fsp: Map FSP debug level to coreboot console level ...................................................................... drivers/intel/fsp: Map FSP debug level to coreboot console level This patch maps coreboot console level to FSP debug level. This is useful to suppress MRC (FSP-M) debug logs. Callers have to select HAVE_DEBUG_RAM_SETUP config to get verbose MRC debug log, Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I398d576fad68a0d0fc931c175bbc04fcbc2e54ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/60471 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/drivers/intel/fsp2_0/debug.c M src/drivers/intel/fsp2_0/include/fsp/debug.h 2 files changed, 47 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Angel Pons: Looks good to me, approved Tim Wawrzynczak: Looks good to me, but someone else must approve diff --git a/src/drivers/intel/fsp2_0/debug.c b/src/drivers/intel/fsp2_0/debug.c index 323c799..130ea6d 100644 --- a/src/drivers/intel/fsp2_0/debug.c +++ b/src/drivers/intel/fsp2_0/debug.c @@ -1,8 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <commonlib/helpers.h> #include <console/console.h> #include <console/streams.h> #include <cpu/x86/mtrr.h> +#include <fsp/debug.h> #include <fsp/util.h> asmlinkage size_t fsp_write_line(uint8_t *buffer, size_t number_of_bytes) @@ -32,6 +34,41 @@ } } +enum fsp_log_level fsp_map_console_log_level(void) +{ + enum fsp_log_level fsp_debug_level; + + switch (get_log_level()) { + case BIOS_EMERG: + case BIOS_ALERT: + case BIOS_CRIT: + case BIOS_ERR: + fsp_debug_level = FSP_LOG_LEVEL_ERR; + break; + case BIOS_WARNING: + fsp_debug_level = FSP_LOG_LEVEL_ERR_WARN; + break; + case BIOS_NOTICE: + fsp_debug_level = FSP_LOG_LEVEL_ERR_WARN_INFO; + break; + case BIOS_INFO: + fsp_debug_level = FSP_LOG_LEVEL_ERR_WARN_INFO_EVENT; + break; + case BIOS_DEBUG: + case BIOS_SPEW: + fsp_debug_level = FSP_LOG_LEVEL_VERBOSE; + break; + default: + fsp_debug_level = FSP_LOG_LEVEL_DISABLE; + break; + } + + if (!CONFIG(DEBUG_RAM_SETUP)) + fsp_debug_level = MIN(fsp_debug_level, FSP_LOG_LEVEL_ERR_WARN); + + return fsp_debug_level; +} + /*----------- * MemoryInit *----------- diff --git a/src/drivers/intel/fsp2_0/include/fsp/debug.h b/src/drivers/intel/fsp2_0/include/fsp/debug.h index be7dd3a..b6f982a 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/debug.h +++ b/src/drivers/intel/fsp2_0/include/fsp/debug.h @@ -5,7 +5,17 @@ #include <fsp/util.h> +enum fsp_log_level { + FSP_LOG_LEVEL_DISABLE = 0, + FSP_LOG_LEVEL_ERR, + FSP_LOG_LEVEL_ERR_WARN, + FSP_LOG_LEVEL_ERR_WARN_INFO, + FSP_LOG_LEVEL_ERR_WARN_INFO_EVENT, + FSP_LOG_LEVEL_VERBOSE +}; + /* FSP debug API */ +enum fsp_log_level fsp_map_console_log_level(void); void fsp_debug_before_memory_init(fsp_memory_init_fn memory_init, const FSPM_UPD *fspm_old_upd, const FSPM_UPD *fspm_new_upd); -- To view, visit https://review.coreboot.org/c/coreboot/+/60471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I398d576fad68a0d0fc931c175bbc04fcbc2e54ec Gerrit-Change-Number: 60471 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake: Add option to make MRC log silent
by Nico Huber (Code Review) 03 Jan '22

03 Jan '22

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60441 ) Change subject: soc/intel/alderlake: Add option to make MRC log silent ...................................................................... soc/intel/alderlake: Add option to make MRC log silent Typically, FSP-M aka MRC debug log level defaults to `3` meaning prints all `Load, Error, Warnings & Info` messages. Sometimes it's too much information to parse even when users aren't required to have such detailed information hence, implement `fsp_map_console_log_level()` that maps coreboot console log level to FSP-M debug log level and suppress verbose MRC debug messages unless caller selects `HAVE_DEBUG_RAM_SETUP` config and then the user can enable `DEBUG_RAM_SETUP`. TEST=FSP-M debug log suggested default `SerialDebugMrcLevel` UPD value is `2`. While this patch selects `HAVE_DEBUG_RAM_SETUP` and user to select `DEBUG_RAM_SETUP` config to override `SerialDebugMrcLevel` UPD value to '5' aka verbose. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Iea3b32feca0893a83fdf700798b0883d26ccc718 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60441 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/romstage/fsp_params.c 2 files changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 0c68351..50c0c0b 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -43,6 +43,7 @@ select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 select FSPS_HAS_ARCH_UPD select GENERIC_GPIO_LIB + select HAVE_DEBUG_RAM_SETUP select HAVE_FSP_GOP select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 8959bf7..0eeaabd 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -312,6 +312,9 @@ static void fill_fspm_trace_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_alderlake_config *config) { + /* Set MRC debug level */ + m_cfg->SerialDebugMrcLevel = fsp_map_console_log_level(); + /* Set debug probe type */ m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_ALDERLAKE_DEBUG_CONSENT; -- To view, visit https://review.coreboot.org/c/coreboot/+/60441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea3b32feca0893a83fdf700798b0883d26ccc718 Gerrit-Change-Number: 60441 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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