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Change subject: mb/google/brya/var/primus: Fix some GPIO programming
......................................................................
Patch Set 22:
(2 comments)
File src/mainboard/google/brya/variants/primus/gpio.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136989):
https://review.coreboot.org/c/coreboot/+/60104/comment/08e4f741_1ac07ad0
PS22, Line 22:
trailing whitespace
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-136989):
https://review.coreboot.org/c/coreboot/+/60104/comment/90cfc6bd_c76d6a76
PS22, Line 22:
please, no spaces at the start of a line
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Hello Felix Singer, build bot (Jenkins), Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/60104
to look at the new patch set (#19).
Change subject: mb/google/brya/var/primus: Fix some GPIO programming
......................................................................
mb/google/brya/var/primus: Fix some GPIO programming
During the initial review, a few unused GPIOs that were inherited
from the baseboard were missed, so this CL programs them as PAD_NC.
GPP_B15 => non-use (for FPR)
GPP_D3 => non-use (Test point)
GPP_E21 => non-use (for LCLW Detect)
BUG=b:211721639
TEST= USE="project_primus" emerge-brya coreboot and verify it builds without error.
Signed-off-by: Ariel_Fang <ariel_fang(a)wistron.corp-partner.google.com>
Change-Id: I4e269bc6fb6eda7b2de57e1a9c900864d3e86e98
---
M src/mainboard/google/brya/variants/primus/gpio.c
M src/mainboard/google/brya/variants/primus4es/gpio.c
2 files changed, 21 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/60104/19
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Joey Peng has uploaded a new patch set (#11) to the change originally created by Kevin Chang. ( https://review.coreboot.org/c/coreboot/+/60341 )
Change subject: mb/google/brya/var/taeko: Add judgement for PCIE signal switch
......................................................................
mb/google/brya/var/taeko: Add judgement for PCIE signal switch
Taeko will use two PCIE port signals with one slot, one CLK and one
CLKREQ. In order to accommodate this, probe statements are added to the
devicetree.
BUG=b:211914322
TEST=Test on takeo trace in FSP log can found setting correct
Cq-Depend: chromium:3358662
Signed-off-by: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com>
Change-Id: I4486f23ea02374c84a9b1ce04f568d78aeabd573
---
M src/mainboard/google/brya/variants/taeko/overridetree.cb
1 file changed, 12 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/60341/11
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Joey Peng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60341 )
Change subject: mb/google/brya/var/taeko: Add judgement for PCIE signal switch
......................................................................
Patch Set 10:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60341/comment/ef9416d4_a0722a2e
PS9, Line 9: singal
> `signal`
Done
https://review.coreboot.org/c/coreboot/+/60341/comment/9bacb196_fda4f795
PS9, Line 10: that need add judgement in overridetree.cb.
> suggestion: […]
Thanks for the advice, updated in latest patch.
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Joey Peng has uploaded a new patch set (#10) to the change originally created by Kevin Chang. ( https://review.coreboot.org/c/coreboot/+/60341 )
Change subject: mb/google/brya/var/taeko: Add judgement for PCIE signal switch
......................................................................
mb/google/brya/var/taeko: Add judgement for PCIE signal switch
Taeko will use two PCIE port signals with one slot, one CLK and one
CLKREQ.In order to accommodate this, probe statements are added to the
devicetree.
BUG=b:211914322
TEST=Test on takeo trace in FSP log can found setting correct
Cq-Depend: chromium:3358662
Signed-off-by: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com>
Change-Id: I4486f23ea02374c84a9b1ce04f568d78aeabd573
---
M src/mainboard/google/brya/variants/taeko/overridetree.cb
1 file changed, 12 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/60341/10
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Joey Peng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60400 )
Change subject: mb/google/brya/var/taeko: Modify DPTF setting for taeko
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60400/comment/8c55144f_1ab45c2c
PS2, Line 9: According to thermal team request modify DPTF setting.
> suggestion: […]
Thanks for the advice,updated in latest patch.
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Change subject: mb/google/brya/var/taeko: Modify DPTF setting for taeko
......................................................................
mb/google/brya/var/taeko: Modify DPTF setting for taeko
The new settings from the thermal team improve performance mainly with
respect to fan control settings.
BRANCH=None
BUG=b:212210824
TEST=Built and tested on taeko board
Signed-off-by: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com>
Change-Id: I2d5c9b6dff87a2e8897d74f3be89c965db22fe16
---
M src/mainboard/google/brya/variants/taeko/overridetree.cb
M src/mainboard/google/brya/variants/taeko4es/overridetree.cb
2 files changed, 36 insertions(+), 36 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/60400/3
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60417 )
Change subject: mb/google/brya/var/primus4es: reconfig USE_PM_ACPI_TIMER
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
This isn't very clear to me yet.
So having USE_PM_ACPI_TIMER set to n will make S0ix work on primus,
but primus4es requires it to be set to y for S0ix to work?
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Change subject: soc/intel: Remove unused <string.h>
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
Hmm, that is a lot of files to verify at one time that shouldn't have string.h included...
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Change subject: mb/google/brya/var/gimble: Decrease touchscreen T3 timing to 200ms
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/brya/variants/gimble/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/60270/comment/09dac23d_9639fa73
PS2, Line 211: register "generic.reset_delay_ms" = "200"
> Can a comment be added, that the spec requires 300 ms, and the heuristic assures, that 300 ms is met […]
👍
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