coreboot-gerrit January 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/brya/var/taeko:Remove duplicate DB_SD fw_config fields.
by Felix Held (Code Review) 05 Jan '22

05 Jan '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60409 ) Change subject: mb/google/brya/var/taeko:Remove duplicate DB_SD fw_config fields. ...................................................................... mb/google/brya/var/taeko:Remove duplicate DB_SD fw_config fields. Since fw config fields for DB_SD can share the same driver, we will remove the duplicate fields DB_SD_GL9750 and DB_SD_RTS5232S. BUG=b:212240358 TEST=emerge-brya coreboot and can boot to OS. Signed-off-by: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Change-Id: If7814c35f63fd6fa27195d448c4d51fc980aaa9c Reviewed-on: https://review.coreboot.org/c/coreboot/+/60409 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/brya/variants/taeko/overridetree.cb M src/mainboard/google/brya/variants/taeko4es/overridetree.cb 2 files changed, 0 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb index 44b9503..5cdc066 100644 --- a/src/mainboard/google/brya/variants/taeko/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb @@ -6,8 +6,6 @@ field DB_SD 2 3 option DB_SD_ABSENT 0 option DB_SD_OZ711LV2LN 1 - option DB_SD_GL9750 2 - option DB_SD_RTS5232S 3 end field KB_BL 4 option KB_BL_ABSENT 0 @@ -391,8 +389,6 @@ register "srcclk_pin" = "3" device generic 0 on probe DB_SD DB_SD_OZ711LV2LN - probe DB_SD DB_SD_GL9750 - probe DB_SD DB_SD_RTS5232S end end end diff --git a/src/mainboard/google/brya/variants/taeko4es/overridetree.cb b/src/mainboard/google/brya/variants/taeko4es/overridetree.cb index 6356661..8aaeab7 100644 --- a/src/mainboard/google/brya/variants/taeko4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko4es/overridetree.cb @@ -6,8 +6,6 @@ field DB_SD 2 3 option DB_SD_ABSENT 0 option DB_SD_OZ711LV2LN 1 - option DB_SD_GL9750 2 - option DB_SD_RTS5232S 3 end field KB_BL 4 option KB_BL_ABSENT 0 @@ -386,8 +384,6 @@ register "srcclk_pin" = "3" device generic 0 on probe DB_SD DB_SD_OZ711LV2LN - probe DB_SD DB_SD_GL9750 - probe DB_SD DB_SD_RTS5232S end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/60409 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7814c35f63fd6fa27195d448c4d51fc980aaa9c Gerrit-Change-Number: 60409 Gerrit-PatchSet: 3 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: util/inteltool: Add support for Tiger Lake chips detection and GPIOs
by Benjamin Doron (Code Review) 05 Jan '22

05 Jan '22

Attention is currently required from: Felix Singer, Wonkyu Kim, Michał Żygowski, Ravishankar Sarawadi, Stefan Reinauer, Angel Pons. Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56171 ) Change subject: util/inteltool: Add support for Tiger Lake chips detection and GPIOs ...................................................................... Patch Set 4: (2 comments) Patchset: PS4: Why File util/inteltool/pcr.c: https://review.coreboot.org/c/coreboot/+/56171/comment/0a1394a6_0cb2b092 PS4, Line 108: case PCI_DEVICE_ID_INTEL_Q570: : case PCI_DEVICE_ID_INTEL_Z590: : case PCI_DEVICE_ID_INTEL_H570: : case PCI_DEVICE_ID_INTEL_B560: : case PCI_DEVICE_ID_INTEL_H510: : case PCI_DEVICE_ID_INTEL_WM590: : case PCI_DEVICE_ID_INTEL_QM580: : case PCI_DEVICE_ID_INTEL_HM570: : case PCI_DEVICE_ID_INTEL_C252: : case PCI_DEVICE_ID_INTEL_C256: : case PCI_DEVICE_ID_INTEL_W580: > TGL-H should be handled the same way as TGL-LP I agree (found via testing). On HM570, dumping GPIOs via MMIO method works and returned data seems generally sane. -- To view, visit https://review.coreboot.org/c/coreboot/+/56171 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6071a999be9e8a372997db0369218f297e579d08 Gerrit-Change-Number: 56171 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Wonkyu Kim Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Wonkyu Kim Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 05 Jan 2022 19:58:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: src: Remove unused <cf9_reset.h>
by HAOUAS Elyes (Code Review) 05 Jan '22

05 Jan '22

Attention is currently required from: Patrick Rudolph. Hello Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60803 to look at the new patch set (#2). Change subject: src: Remove unused <cf9_reset.h> ...................................................................... src: Remove unused <cf9_reset.h> Found using: diff <(git grep -l '#include <cf9_reset.h>' -- src/) <(git grep -l 'RST_CNT\|FULL_RST\|RST_CPU\|SYS_RST\|do_system_reset\|do_full_reset\|cf9_reset_prepare\|system_reset\|full_reset' -- src/) |grep "<" Change-Id: I093d8412e14ce81b462fb9a7ccb3a2a93ae760a6 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/intel/dcp847ske/early_southbridge.c M src/mainboard/roda/rk886ex/early_init.c M src/northbridge/intel/ironlake/romstage.c M src/security/intel/txt/romstage.c M src/soc/intel/broadwell/romstage.c M src/soc/intel/common/block/acpi/acpi.c 6 files changed, 0 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/60803/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60803 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I093d8412e14ce81b462fb9a7ccb3a2a93ae760a6 Gerrit-Change-Number: 60803 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src: REmove unused <cf9_reset.h>
by HAOUAS Elyes (Code Review) 05 Jan '22

05 Jan '22

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60803 ) Change subject: src: REmove unused <cf9_reset.h> ...................................................................... src: REmove unused <cf9_reset.h> Found using: diff <(git grep -l '#include <cf9_reset.h>' -- src/) <(git grep -l 'RST_CNT\|FULL_RST\|RST_CPU\|SYS_RST\|do_system_reset\|do_full_reset\|cf9_reset_prepare\|system_reset\|full_reset' -- src/) |grep "<" Change-Id: I093d8412e14ce81b462fb9a7ccb3a2a93ae760a6 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/intel/dcp847ske/early_southbridge.c M src/mainboard/roda/rk886ex/early_init.c M src/northbridge/intel/ironlake/romstage.c M src/security/intel/txt/romstage.c M src/soc/intel/broadwell/romstage.c M src/soc/intel/common/block/acpi/acpi.c 6 files changed, 0 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/60803/1 diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c index 92d49c1..e2fd2aa 100644 --- a/src/mainboard/intel/dcp847ske/early_southbridge.c +++ b/src/mainboard/intel/dcp847ske/early_southbridge.c @@ -2,7 +2,6 @@ #include <bootblock_common.h> #include <stdint.h> -#include <cf9_reset.h> #include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> diff --git a/src/mainboard/roda/rk886ex/early_init.c b/src/mainboard/roda/rk886ex/early_init.c index 76471eb..ddea82f 100644 --- a/src/mainboard/roda/rk886ex/early_init.c +++ b/src/mainboard/roda/rk886ex/early_init.c @@ -3,7 +3,6 @@ #include <bootblock_common.h> #include <stdint.h> #include <arch/io.h> -#include <cf9_reset.h> #include <device/pnp_ops.h> #include <device/pci_ops.h> #include <device/pci_def.h> diff --git a/src/northbridge/intel/ironlake/romstage.c b/src/northbridge/intel/ironlake/romstage.c index 8d3cfd6..5214b53 100644 --- a/src/northbridge/intel/ironlake/romstage.c +++ b/src/northbridge/intel/ironlake/romstage.c @@ -3,7 +3,6 @@ #include <arch/io.h> #include <stdint.h> #include <console/console.h> -#include <cf9_reset.h> #include <device/pci_ops.h> #include <cpu/x86/lapic.h> #include <timestamp.h> diff --git a/src/security/intel/txt/romstage.c b/src/security/intel/txt/romstage.c index 98308b7..e045c9d 100644 --- a/src/security/intel/txt/romstage.c +++ b/src/security/intel/txt/romstage.c @@ -2,7 +2,6 @@ #include <arch/cpu.h> #include <arch/mmio.h> -#include <cf9_reset.h> #include <console/console.h> #include <cpu/intel/common/common.h> #include <cpu/x86/cr.h> diff --git a/src/soc/intel/broadwell/romstage.c b/src/soc/intel/broadwell/romstage.c index 09a7283..75563cd 100644 --- a/src/soc/intel/broadwell/romstage.c +++ b/src/soc/intel/broadwell/romstage.c @@ -3,7 +3,6 @@ #include <acpi/acpi.h> #include <arch/romstage.h> #include <cbmem.h> -#include <cf9_reset.h> #include <console/console.h> #include <cpu/intel/haswell/haswell.h> #include <elog.h> diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index b827c58..4493c33 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -5,7 +5,6 @@ #include <arch/cpu.h> #include <arch/ioapic.h> #include <arch/smp/mpspec.h> -#include <cf9_reset.h> #include <console/console.h> #include <cpu/intel/turbo.h> #include <cpu/intel/msr.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/60803 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I093d8412e14ce81b462fb9a7ccb3a2a93ae760a6 Gerrit-Change-Number: 60803 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/gpio: Rework PAD config macro to add lock support
by Subrata Banik (Code Review) 05 Jan '22

05 Jan '22

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Nick Vaccaro, Angel Pons, Meera Ravindranath, Patrick Rudolph, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60774 ) Change subject: soc/intel/common/gpio: Rework PAD config macro to add lock support ...................................................................... Patch Set 4: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/60774/comment/38bac066_213a121e PS3, Line 10: to > space Ack File src/soc/intel/common/block/gpio/gpio.c: https://review.coreboot.org/c/coreboot/+/60774/comment/37404823_2e045442 PS4, Line 345: gpio_lock_pad(cfg->pad, cfg->action); > Doesn't this need to run in SMM? Ideally you don't need to run unlock to lock operation in SMM mode. But if you are programming lock config at the later stage when sideband access restriction is applied (after postboot_sai), then only way to use sideband access is inside SMM. With this CL, we are pulling PAD lock configuration prior to FSP-S as part of GPIO PAD config so, hopefully we don't need to use SBI. (Eric is helping me on debug/enabling this 😊) Although GPIO BWG (doc: 630603) recommends to perform lock to unlock operation inside SMM. But it also says, one can even perform this operation outside SMM as well, `Unlock the GPIO PIN, configure the desired value and then lock it again prior to enabling SMI using non-SMM code.` File src/soc/intel/common/block/include/intelblocks/gpio.h: https://review.coreboot.org/c/coreboot/+/60774/comment/40772bb4_d9092d66 PS3, Line 79: gpio_lock_action action > use tab to align this Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/60774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf8b0a845005ad545266d995449d0aa711f45a61 Gerrit-Change-Number: 60774 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Wed, 05 Jan 2022 19:30:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/gpio: Rework PAD config macro to add lock support
by Subrata Banik (Code Review) 05 Jan '22

05 Jan '22

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Nick Vaccaro, Angel Pons, Meera Ravindranath, Patrick Rudolph, EricR Lai. Hello build bot (Jenkins), Maulik V Vaghela, Tim Wawrzynczak, Nick Vaccaro, Angel Pons, Meera Ravindranath, Patrick Rudolph, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60774 to look at the new patch set (#5). Change subject: soc/intel/common/gpio: Rework PAD config macro to add lock support ...................................................................... soc/intel/common/gpio: Rework PAD config macro to add lock support This patch creates new GPIO PAD configuration macros that would help to perform GPIO pad configuration and pad lock configuration as well. Lists of new macros are: 1. PAD_CFG_NF_LOCK 2. PAD_CFG_GPO_LOCK 3. PAD_CFG_GPI_LOCK 4. PAD_CFG_GPI_TRIG_OWN_LOCK 5. PAD_CFG_GPI_GPIO_DRIVER_LOCK 6. PAD_CFG_GPI_INT_LOCK 7. PAD_CFG_GPI_APIC_LOCK 8. PAD_CFG_GPI_IRQ_WAKE_LOCK Mainboard users can use the above macros to lock the PAD after configuration. So far on IA chipset. the default GPIO pad lock configuration reset type is POWERGOOD hence, its recommended as per GPIO BWG (doc: 630603) to configure the GPP PAD reset type as same as lock configuration reset type to avoid GPP reset value misconfiguration issue. BUG=b:211573253, b:211950520 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ibf8b0a845005ad545266d995449d0aa711f45a61 --- M src/soc/intel/common/block/gpio/gpio.c M src/soc/intel/common/block/include/intelblocks/gpio.h M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 3 files changed, 81 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/60774/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/60774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf8b0a845005ad545266d995449d0aa711f45a61 Gerrit-Change-Number: 60774 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [TESTONLY] spd_bin.h: Drop `len` field
by Angel Pons (Code Review) 05 Jan '22

05 Jan '22

Angel Pons has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/60799 ) Change subject: [TESTONLY] spd_bin.h: Drop `len` field ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/60799 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia3b4b70d73a0462f4d8c028978a03be798d0ceea Gerrit-Change-Number: 60799 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: soc/intel/common/blk/memory: Make mixed topo work
by Tim Crawford (Code Review) 05 Jan '22

05 Jan '22

Attention is currently required from: Tim Wawrzynczak, Angel Pons, Patrick Rudolph. Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60800 ) Change subject: soc/intel/common/blk/memory: Make mixed topo work ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: Tested on system76/lemp10. Unit boots with and without DIMM installed. -- To view, visit https://review.coreboot.org/c/coreboot/+/60800 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1cabf64fade1c06a44b6c3892659d54febc7a79a Gerrit-Change-Number: 60800 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 05 Jan 2022 19:11:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/gpio: Skip GPP pad lock config if config is not set
by Subrata Banik (Code Review) 05 Jan '22

05 Jan '22

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Nick Vaccaro, Meera Ravindranath, Patrick Rudolph, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60776 ) Change subject: soc/intel/common/gpio: Skip GPP pad lock config if config is not set ...................................................................... Patch Set 3: (1 comment) Patchset: PS2: > yes @Eric, my analysis with #ifdef/#endif, the code size reduction is not very significant compare to how much of #ifdef/#endif we might need to guard like `sideband_msg_err`. Also, long back Aaron told me once to avoid guarding functions if its not getting executed then compiler would optimise it. WDYT? just if clause is enough? -- To view, visit https://review.coreboot.org/c/coreboot/+/60776 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I392dc2007dba8169e480f82b58b7f0a1578bb09f Gerrit-Change-Number: 60776 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Wed, 05 Jan 2022 19:05:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/gpio: Perform GPIO PAD lock outside SMM
by Subrata Banik (Code Review) 05 Jan '22

05 Jan '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60801 ) Change subject: soc/intel/common/gpio: Perform GPIO PAD lock outside SMM ...................................................................... soc/intel/common/gpio: Perform GPIO PAD lock outside SMM This patch performs GPIO PAD lock configuration in non-smm mode. Typically, coreboot enables SMI at latest boot phase post FSP-S, hence, FSP-S might get chance to perform GPP lock configuration. With this code changes, coreboot can be able to perform GPIO PAD lock configuration early in the boot flow, prior to calling FSP-S. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I71b4e2f24303b6acb56debd581bd6bc818b6f926 --- M src/soc/intel/common/block/gpio/gpio.c 1 file changed, 47 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/60801/1 diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index 419c77e..8953667 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -552,8 +552,55 @@ return err_response; } +static void +gpio_rmw32(gpio_t gpio_num, uint16_t offset, uint32_t anddata, uint32_t ordata) +{ + const struct pad_community *comm = gpio_get_community(gpio_num); + + pcr_rmw32(comm->port, offset, anddata, ordata); +} + +static int gpio_non_smm_lock_pad(gpio_t gpio_num, enum gpio_lock_action action) +{ + const struct pad_community *comm = gpio_get_community(gpio_num); + uint16_t offset; + size_t rel_pad; + uint32_t data; + + rel_pad = relative_pad_in_comm(comm, gpio_num); + offset = comm->pad_cfg_lock_offset; + if (!offset) { + printk(BIOS_ERR, "%s: Error: offset not defined for pad %d!\n", + __func__, gpio_num); + return -1; + } + + offset += gpio_group_index_scaled(comm, rel_pad, 2 * sizeof(uint32_t)); + data = gpio_bitmask_within_group(comm, rel_pad); + + switch (action) { + case GPIO_LOCK_CONFIG: + gpio_rmw32(gpio_num, offset, ~0, data); + break; + case GPIO_LOCK_TX: + gpio_rmw32(gpio_num, offset + 4, ~0, data); + break; + case GPIO_LOCK_FULL: + gpio_rmw32(gpio_num, offset, ~0, data); + gpio_rmw32(gpio_num, offset + 4, ~0, data); + break; + default: + break; + } + + return 0; +} + int gpio_lock_pad(const gpio_t pad, enum gpio_lock_action action) { + if (!CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS)) + return gpio_non_smm_lock_pad(pad, action); + const struct gpio_lock_config pads = { .pad = pad, .action = action -- To view, visit https://review.coreboot.org/c/coreboot/+/60801 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71b4e2f24303b6acb56debd581bd6bc818b6f926 Gerrit-Change-Number: 60801 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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