coreboot-gerrit January 2022

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Change in coreboot[master]: libpayload: Parse DDR Information through coreboot tables
by build bot (Jenkins) (Code Review) 05 Jan '22

05 Jan '22

Attention is currently required from: Ravi kumar, Shelley Chen, mturney mturney, Sudheer Amrabadi, Julius Werner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59193 ) Change subject: libpayload: Parse DDR Information through coreboot tables ...................................................................... Patch Set 10: (1 comment) File payloads/libpayload/include/mem_chip_info.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-137368): https://review.coreboot.org/c/coreboot/+/59193/comment/63e57187_97ee7e1e PS10, Line 44: }dram_info; space required after that close brace '}' -- To view, visit https://review.coreboot.org/c/coreboot/+/59193 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieca7e9fc0e1a018fcb2e9315aebee088edac858e Gerrit-Change-Number: 59193 Gerrit-PatchSet: 10 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-Comment-Date: Wed, 05 Jan 2022 18:23:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [TESTONLY] spd_bin.h: Drop `len` field
by Angel Pons (Code Review) 05 Jan '22

05 Jan '22

Attention is currently required from: Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60799 ) Change subject: [TESTONLY] spd_bin.h: Drop `len` field ...................................................................... Patch Set 1: Code-Review-2 (1 comment) Patchset: PS1: Just trying to see if we use this field anywhere else. -- To view, visit https://review.coreboot.org/c/coreboot/+/60799 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia3b4b70d73a0462f4d8c028978a03be798d0ceea Gerrit-Change-Number: 60799 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 05 Jan 2022 18:12:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [TESTONLY] spd_bin.h: Drop `len` field
by Angel Pons (Code Review) 05 Jan '22

05 Jan '22

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60799 ) Change subject: [TESTONLY] spd_bin.h: Drop `len` field ...................................................................... [TESTONLY] spd_bin.h: Drop `len` field Change-Id: Ia3b4b70d73a0462f4d8c028978a03be798d0ceea Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/include/spd_bin.h M src/soc/intel/common/block/memory/meminit.c M src/soc/intel/common/block/smbus/smbuslib.c 3 files changed, 1 insertion(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/60799/1 diff --git a/src/include/spd_bin.h b/src/include/spd_bin.h index 973eb49..a72f831 100644 --- a/src/include/spd_bin.h +++ b/src/include/spd_bin.h @@ -38,8 +38,6 @@ struct spd_block { u8 addr_map[CONFIG_DIMM_MAX]; /* 7 bit I2C addresses */ u8 *spd_array[CONFIG_DIMM_MAX]; - /* Length of each dimm */ - u16 len; }; void print_spd_info(uint8_t spd[]); diff --git a/src/soc/intel/common/block/memory/meminit.c b/src/soc/intel/common/block/memory/meminit.c index 50c8b40..9b1f326 100644 --- a/src/soc/intel/common/block/memory/meminit.c +++ b/src/soc/intel/common/block/memory/meminit.c @@ -119,7 +119,7 @@ } get_spd_smbus(&blk); - *spd_len = blk.len; + *spd_len = CONFIG_DIMM_SPD_SIZE; for (ch = 0; ch < num_phys_ch; ch++) { size_t mrc_ch = soc_mem_cfg->phys_to_mrc_map[ch]; diff --git a/src/soc/intel/common/block/smbus/smbuslib.c b/src/soc/intel/common/block/smbus/smbuslib.c index 17b6377..30d014d 100644 --- a/src/soc/intel/common/block/smbus/smbuslib.c +++ b/src/soc/intel/common/block/smbus/smbuslib.c @@ -6,20 +6,6 @@ #include <device/smbus_host.h> #include "smbuslib.h" -static void update_spd_len(struct spd_block *blk) -{ - u8 i, j = 0; - for (i = 0 ; i < CONFIG_DIMM_MAX; i++) - if (blk->spd_array[i] != NULL) - j |= blk->spd_array[i][SPD_DRAM_TYPE]; - - /* If spd used is DDR4, then its length is 512 byte. */ - if (j == SPD_DRAM_DDR4) - blk->len = SPD_PAGE_LEN_DDR4; - else - blk->len = SPD_PAGE_LEN; -} - static void smbus_read_spd(u8 *spd, u8 addr) { u16 i; @@ -83,8 +69,6 @@ else blk->spd_array[i] = NULL; } - - update_spd_len(blk); } /* -- To view, visit https://review.coreboot.org/c/coreboot/+/60799 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia3b4b70d73a0462f4d8c028978a03be798d0ceea Gerrit-Change-Number: 60799 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sc7280: Add Modem region in memlayout to avoid modem cleanup in Secbo...
by build bot (Jenkins) (Code Review) 05 Jan '22

05 Jan '22

Attention is currently required from: Ravi kumar, Sudheer Amrabadi. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58545 ) Change subject: sc7280: Add Modem region in memlayout to avoid modem cleanup in Secboot reboot. ...................................................................... Patch Set 15: (1 comment) File src/soc/qualcomm/sc7280/soc.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-137365): https://review.coreboot.org/c/coreboot/+/58545/comment/464885c9_641dda90 PS15, Line 27: if (soc_modem_carve_out(&start, &end)) that open brace { should be on the previous line -- To view, visit https://review.coreboot.org/c/coreboot/+/58545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56bfb210606b08893ff71dd1b6679f1ec102ec95 Gerrit-Change-Number: 58545 Gerrit-PatchSet: 15 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Comment-Date: Wed, 05 Jan 2022 18:08:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: xcompile: Support i686-elf toolchains
by Martin Roth (Code Review) 05 Jan '22

05 Jan '22

Attention is currently required from: Patrick Georgi, Stefan Reinauer, Paul Menzel, Alex James. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60218 ) Change subject: xcompile: Support i686-elf toolchains ...................................................................... Patch Set 3: (1 comment) Patchset: PS2: > I see. I can drop this change if it doesn't make sense to include it. The other possibility is to make sure that everything is configured and enabled correctly in the asm code before we jump to the C code. Also, while we do allow building with other compilers, we'd strongly recommend building with the coreboot toolchain. That keeps it compatible with other people in the community and helps to cut down on problems from the random toolchains that may be installed on everyone's systems. -- To view, visit https://review.coreboot.org/c/coreboot/+/60218 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdf2cdd8b244822740c03935747184ebc5ca1512 Gerrit-Change-Number: 60218 Gerrit-PatchSet: 3 Gerrit-Owner: Alex James <theracermaster(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Alex James <theracermaster(a)gmail.com> Gerrit-Comment-Date: Wed, 05 Jan 2022 18:02:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Comment-In-Reply-To: Alex James <theracermaster(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/primus: Fix some GPIO programming
by 9elements QA (Code Review) 05 Jan '22

05 Jan '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60104 ) Change subject: mb/google/brya/var/primus: Fix some GPIO programming ...................................................................... Patch Set 30: Automatic boot test returned (PASS/FAIL/TOTAL): 9 / 1 / 10 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/87768 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/87767 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/87766 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/87765 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/87764 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/87763 FAIL: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/87762 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/87761 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/87760 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/87759 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/60104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e269bc6fb6eda7b2de57e1a9c900864d3e86e98 Gerrit-Change-Number: 60104 Gerrit-PatchSet: 30 Gerrit-Owner: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-Comment-Date: Wed, 05 Jan 2022 18:01:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Revert "libpayload/libc/fmap: Implement new FlashMap API"
by Jakub Czapiga (Code Review) 05 Jan '22

05 Jan '22

Attention is currently required from: Sudheer Amrabadi. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60797 ) Change subject: Revert "libpayload/libc/fmap: Implement new FlashMap API" ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: May I ask, why do you want to revert this commit? -- To view, visit https://review.coreboot.org/c/coreboot/+/60797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieccf2d709206e1cb53fec00d0fafb3748b9dedb6 Gerrit-Change-Number: 60797 Gerrit-PatchSet: 1 Gerrit-Owner: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Comment-Date: Wed, 05 Jan 2022 17:51:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Fix GPIO reset mapping as per GPIO BWG
by Subrata Banik (Code Review) 05 Jan '22

05 Jan '22

Attention is currently required from: Maulik V Vaghela, Meera Ravindranath, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60789 ) Change subject: soc/intel/alderlake: Fix GPIO reset mapping as per GPIO BWG ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/60789/comment/9c17ae33_1932ad10 PS1, Line 10: - > nit: stray `-` Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/60789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b8742c7a0cc1dc420e3e22e34a16355294ed61b Gerrit-Change-Number: 60789 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 05 Jan 2022 17:49:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: payloads/tianocore: Add option to enable SMM Support
by Sean Rhodes (Code Review) 05 Jan '22

05 Jan '22

Sean Rhodes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60798 ) Change subject: payloads/tianocore: Add option to enable SMM Support ...................................................................... payloads/tianocore: Add option to enable SMM Support Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: Id262235610ef350994da7373784e2f6bbab65da6 --- M payloads/external/Makefile.inc M payloads/external/tianocore/Kconfig M payloads/external/tianocore/Makefile 3 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/60798/1 diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index a6c7305..9430e33 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -154,6 +154,7 @@ CONFIG_TIANOCORE_COREBOOTPAYLOAD=$(CONFIG_TIANOCORE_COREBOOTPAYLOAD) \ CONFIG_TIANOCORE_FOLLOW_BGRT_SPEC=$(CONFIG_TIANOCORE_FOLLOW_BGRT_SPEC) \ CONFIG_TIANOCORE_HAVE_EFI_SHELL=$(CONFIG_TIANOCORE_HAVE_EFI_SHELL) \ + CONFIG_TIANOCORE_SMM_SUPPORT=$(CONFIG_TIANOCORE_SMM_SUPPORT) \ CONFIG_TIANOCORE_SECUREBOOT=$(CONFIG_TIANOCORE_SECUREBOOT) \ CONFIG_TIANOCORE_USE_8254_TIMER=$(CONFIG_TIANOCORE_USE_8254_TIMER) \ GCC_CC_x86_32=$(GCC_CC_x86_32) \ diff --git a/payloads/external/tianocore/Kconfig b/payloads/external/tianocore/Kconfig index 67f1437..225cc32 100644 --- a/payloads/external/tianocore/Kconfig +++ b/payloads/external/tianocore/Kconfig @@ -136,6 +136,13 @@ help Include the EFI shell Binary +config TIANOCORE_SMM_SUPPORT + bool "SMM Support in EDK2" + default n + help + Invoke SMM in EDK2, which triggers devices to transition from + PCI mode to ACPI mode + endif if TIANOCORE_COREBOOTPAYLOAD diff --git a/payloads/external/tianocore/Makefile b/payloads/external/tianocore/Makefile index e45455d..0dc8e92 100644 --- a/payloads/external/tianocore/Makefile +++ b/payloads/external/tianocore/Makefile @@ -64,6 +64,10 @@ BGRT=-D FOLLOW_BGRT_SPEC=TRUE endif +ifeq ($(CONFIG_TIANOCORE_SMM_SUPPORT),y) +SMM=-D SMM_SUPPORT=TRUE +endif + PS2=-D PS2_KEYBOARD_ENABLE=TRUE -D SIO_BUS_ENABLE=TRUE TIMEOUT=-D PLATFORM_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT) -- To view, visit https://review.coreboot.org/c/coreboot/+/60798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id262235610ef350994da7373784e2f6bbab65da6 Gerrit-Change-Number: 60798 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/sarien: Add VBT extracted from Chrome OS
by Tim Wawrzynczak (Code Review) 05 Jan '22

05 Jan '22

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60735 ) Change subject: mb/google/sarien: Add VBT extracted from Chrome OS ...................................................................... mb/google/sarien: Add VBT extracted from Chrome OS The VBT is extracted from Chromium OS in developer mode with the device running firwmare . $ sudo dmesg | grep ' DMI:' [ 0.000000] DMI: Dell Inc. Sarien/Sarien, BIOS Google_Sarien.12200.99.0 07/29/2020 $ sudo cbmem -1 coreboot-v1.9308_26_0.0.22-8761-gdba94f429a Wed Jul 29 16:09:30 UTC 2020 bootblock starting (log level: 8)... […] coreboot-v1.9308_26_0.0.22-8761-gdba94f429a Wed Jul 29 16:09:30 UTC 2020 ramstage starting (log level: 8)... […] CBFS: Locating 'vbt.bin' CBFS: Found @ offset 614c0 size 4a0 Found a VBT of 4608 bytes after decompression […] $ sudo cp /sys/kernel/debug/dri/0/i915_vbt vbt.bin Using the Chrome OS recovery image, Matt DeVillier verified, that the Sarien VBT is identical to Arcada, so add the VBT for all variants. Change-Id: Ibab8a7b0b3f721ca434ac38b51528b81e66f3bb7 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60735 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/sarien/Kconfig A src/mainboard/google/sarien/data.vbt 2 files changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved Angel Pons: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig index 42c3aba..d58f64d 100644 --- a/src/mainboard/google/sarien/Kconfig +++ b/src/mainboard/google/sarien/Kconfig @@ -10,6 +10,7 @@ select GOOGLE_SMBIOS_MAINBOARD_VERSION select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_I2C_TPM_CR50 @@ -91,4 +92,9 @@ select HAS_RECOVERY_MRC_CACHE select VBOOT_LID_SWITCH +# Override the default variant behavior, since the data.vbt is the same +# for all variants. +config INTEL_GMA_VBT_FILE + default "src/mainboard/\$(MAINBOARDDIR)/data.vbt" + endif # BOARD_GOOGLE_BASEBOARD_SARIEN diff --git a/src/mainboard/google/sarien/data.vbt b/src/mainboard/google/sarien/data.vbt new file mode 100644 index 0000000..f9c498e --- /dev/null +++ b/src/mainboard/google/sarien/data.vbt Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/60735 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibab8a7b0b3f721ca434ac38b51528b81e66f3bb7 Gerrit-Change-Number: 60735 Gerrit-PatchSet: 5 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit January 2022