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Change subject: soc/intel/common/gpio: Rework PAD config macro to add lock support
......................................................................
Patch Set 4:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/gpio_defs.h:
https://review.coreboot.org/c/coreboot/+/60774/comment/ffa07aff_92be07ac
PS4, Line 203: PWROK
> I see, thanks for the explanation. Would be good to document this somewhere.
You can find this description in doc 630603 (as mentioned by Intel)
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Change subject: mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F
......................................................................
Patch Set 72:
(1 comment)
File Documentation/mainboard/supermicro/x11-lga1151v2-series/x11sch-f/x11sch-f.md:
https://review.coreboot.org/c/coreboot/+/37441/comment/6e7e28b6_e19f854e
PS64, Line 31: 0x235=03 and 0x13E=84
> So.... where do your offset/value pairs come from?
They're not mine, I don't know where they come from 😅
@Christian, any clues?
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Change subject: payloads/tianocore: Add option to disable EFI Shell
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/intel/common/gpio: Rework PAD config macro to add lock support
......................................................................
Patch Set 4:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/gpio_defs.h:
https://review.coreboot.org/c/coreboot/+/60774/comment/ee334321_04e99ac8
PS4, Line 203: PWROK
> @Angel, there is a design gap between GPIO PAD reset type and PAD lock configuration reset type. […]
I see, thanks for the explanation. Would be good to document this somewhere.
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Change subject: HACK sc7280: QSIP SPI NOR addressing mode for SKU1 and SKU2 HACK
......................................................................
Patch Set 102:
(4 comments)
File src/drivers/spi/spi_flash.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-137372):
https://review.coreboot.org/c/coreboot/+/50586/comment/7f4d60ce_ee29983b
PS102, Line 533: while (1)
suspect code indent for conditional statements (24, 24)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-137372):
https://review.coreboot.org/c/coreboot/+/50586/comment/74595a33_a7a53588
PS102, Line 554: while (1)
suspect code indent for conditional statements (24, 24)
File src/soc/qualcomm/common/qclib.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-137372):
https://review.coreboot.org/c/coreboot/+/50586/comment/95c2adae_4e676aea
PS102, Line 254: mainboard_blob_fix();
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-137372):
https://review.coreboot.org/c/coreboot/+/50586/comment/4ad11f1b_15c69e8c
PS102, Line 254: mainboard_blob_fix();
please, no spaces at the start of a line
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Change subject: payloads/tianocore: Add option to use F7 as Boot Manager key
......................................................................
Patch Set 3: Code-Review+2
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Change subject: payloads/tianocore: Don't specify default values
......................................................................
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Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60800 )
Change subject: soc/intel/common/blk/memory: Make mixed topo work
......................................................................
soc/intel/common/blk/memory: Make mixed topo work
When using a mixed memory topology with DDR4, it's not possible to boot
when no DIMMs are installed, even though memory-down is available. This
happens because the DIMM SPD length defaults to 256 when no DIMM SPD is
available. Relax the length check when no DIMMs are present to overcome
this problem.
Change-Id: I1cabf64fade1c06a44b6c3892659d54febc7a79a
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/soc/intel/common/block/memory/meminit.c
1 file changed, 10 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/60800/1
diff --git a/src/soc/intel/common/block/memory/meminit.c b/src/soc/intel/common/block/memory/meminit.c
index 50c8b40..78dc2d4 100644
--- a/src/soc/intel/common/block/memory/meminit.c
+++ b/src/soc/intel/common/block/memory/meminit.c
@@ -6,6 +6,7 @@
#include <commonlib/region.h>
#include <spd_bin.h>
#include <string.h>
+#include <types.h>
_Static_assert(CONFIG_MRC_CHANNEL_WIDTH > 0, "MRC channel width must be >0!");
_Static_assert(CONFIG_DATA_BUS_WIDTH > 0, "Data bus width must be >0!");
@@ -93,7 +94,7 @@
#define CH_DIMM_OFFSET(ch, dimm) ((ch) * CONFIG_DIMMS_PER_CHANNEL + (dimm))
-static void read_spd_dimm(const struct soc_mem_cfg *soc_mem_cfg, const struct mem_spd *info,
+static bool read_spd_dimm(const struct soc_mem_cfg *soc_mem_cfg, const struct mem_spd *info,
bool half_populated, struct mem_channel_data *channel_data,
size_t *spd_len)
{
@@ -109,7 +110,7 @@
uint32_t pop_mask = 0;
if (!(info->topo & MEM_TOPO_DIMM_MODULE))
- return;
+ return false;
for (ch = 0; ch < num_phys_ch; ch++) {
for (dimm = 0; dimm < CONFIG_DIMMS_PER_CHANNEL; dimm++) {
@@ -137,6 +138,8 @@
}
channel_data->ch_population_flags |= populated_mask_to_flag(pop_mask, num_phys_ch);
+
+ return pop_mask != 0;
}
void mem_populate_channel_data(const struct soc_mem_cfg *soc_mem_cfg,
@@ -145,11 +148,12 @@
struct mem_channel_data *data)
{
size_t spd_md_len = 0, spd_dimm_len = 0;
+ bool have_dimms;
memset(data, 0, sizeof(*data));
read_spd_md(soc_mem_cfg, spd_info, half_populated, data, &spd_md_len);
- read_spd_dimm(soc_mem_cfg, spd_info, half_populated, data, &spd_dimm_len);
+ have_dimms = read_spd_dimm(soc_mem_cfg, spd_info, half_populated, data, &spd_dimm_len);
if (data->ch_population_flags == NO_CHANNEL_POPULATED)
die("No channels are populated. Incorrect memory configuration!\n");
@@ -161,11 +165,12 @@
} else {
/*
* SPD lengths must match for CBFS and EEPROM SPD for mixed
- * topology.
+ * topology. Skip this check when no DIMMs are installed.
*/
- if (spd_md_len != spd_dimm_len)
+ if (have_dimms && spd_md_len != spd_dimm_len)
die("Length of SPD does not match for mixed topology!\n");
+ /* Use memory-down SPD length in case there are no DIMMs installed */
data->spd_len = spd_md_len;
}
}
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Change subject: mb/google/herobrine: Add support for audio
......................................................................
Patch Set 34:
(7 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/57449/comment/73061f8d_17f46b2f
PS29, Line 7: Herobrine
> mb/google/herobrine
Ack
https://review.coreboot.org/c/coreboot/+/57449/comment/033f4c3a_d9da2420
PS29, Line 7: Herobrine: sc7280: Add support for audio
> … and TPM?
Ack
https://review.coreboot.org/c/coreboot/+/57449/comment/788c3fef_f4b2ce62
PS29, Line 7: sc7280:
> Not needed.
Ack
https://review.coreboot.org/c/coreboot/+/57449/comment/c53451b7_3e05e270
PS29, Line 9: Add gpio configuration for target specific i2s ports
> 1. Please add a dot/period at the end of the line. […]
Ack
Commit Message:
https://review.coreboot.org/c/coreboot/+/57449/comment/daac4ad0_d4bb614b
PS32, Line 7: mb/google/herobrine :
> Please remove the space.
Ack
Patchset:
PS34:
updated related comments
File src/mainboard/google/herobrine/mainboard.c:
https://review.coreboot.org/c/coreboot/+/57449/comment/de11f550_d33e4495
PS28, Line 43:
> No blank line needed.
Ack
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Change subject: mb/google/herobrine: Add support for audio
......................................................................
mb/google/herobrine: Add support for audio
Add GPIO configuration for target specific i2s ports.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 developement board
Signed-off-by: Srinivasa Rao Mandadapu <srivasam(a)codeaurora.org>
Change-Id: I2ce95332f892d5d4acb2755307df84d37feb8002
---
M src/mainboard/google/herobrine/board.h
M src/mainboard/google/herobrine/chromeos.c
M src/mainboard/google/herobrine/mainboard.c
3 files changed, 27 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/57449/34
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