Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56785
to look at the new patch set (#4).
Change subject: sb/amd/pi/hudson: drop HUDSON_UART option and corresponding code
......................................................................
sb/amd/pi/hudson: drop HUDSON_UART option and corresponding code
This option is neither selected nor usable for the only remaining SoC
that uses this code, so drop the remaining parts. configure_hudson_uart
isn't called anywhere and isn't even compiled, since it's guarded by an
#if CONFIG(HUDSON_UART) block and the HUDSON_UART Kconfig option isn't
selected anywhere. Both the offsets used in the iomux_write8 calls and
the UART controller itself aren't listed in the BKDG #52740 Rev 3.05 for
the AMD Family 16h Models 30h-3Fh APUs which is the only SoC that uses
this code, so the code didn't even apply for this chip.
TEST=Timeless build for pcengines/apu2 results in identical binary.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I3f462d1f83a0f1ba851329ebebb1f3263267fdc6
---
M src/southbridge/amd/pi/hudson/Kconfig
M src/southbridge/amd/pi/hudson/Makefile.inc
M src/southbridge/amd/pi/hudson/early_setup.c
M src/southbridge/amd/pi/hudson/hudson.h
D src/southbridge/amd/pi/hudson/uart.c
5 files changed, 0 insertions(+), 59 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/56785/4
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I3f462d1f83a0f1ba851329ebebb1f3263267fdc6
Gerrit-Change-Number: 56785
Gerrit-PatchSet: 4
Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-MessageType: newpatchset
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56809 )
Change subject: sb/amd/pi/hudson/soc/gpio: add SOC_GPIO_TOTAL_PINS definition
......................................................................
sb/amd/pi/hudson/soc/gpio: add SOC_GPIO_TOTAL_PINS definition
EGPIO132 is the last documented GPIO on the GPIO controller in the NDA
version of the BKDG for AMD Family 16h Models 30h-3Fh Processors (#52740
Rev 3.06) which is the only SoC using this code, so define
SOC_GPIO_TOTAL_PINS as 133, since the internal GPIO numbers are
0-indexed. This definition will be needed the subsequent patch that'll
add the remote GPIO support to the common AMD GPIO code to make sure
that the compiler can optimize out the code path needed to support the
remote GPIO access which isn't available on this platform anyway.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I877d462c5e753c9bbb3461dbb10cde2adc2cb12c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56809
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Martin Roth <martinroth(a)google.com>
---
M src/southbridge/amd/pi/hudson/soc/gpio.h
1 file changed, 2 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Martin Roth: Looks good to me, approved
diff --git a/src/southbridge/amd/pi/hudson/soc/gpio.h b/src/southbridge/amd/pi/hudson/soc/gpio.h
index 10a47cb..6069ee0 100644
--- a/src/southbridge/amd/pi/hudson/soc/gpio.h
+++ b/src/southbridge/amd/pi/hudson/soc/gpio.h
@@ -6,4 +6,6 @@
/* <soc/gpio.h> must provide gpio_t. */
#include <amdblocks/gpio_banks.h>
+#define SOC_GPIO_TOTAL_PINS 133
+
#endif /* SOC_GPIO_H */
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I877d462c5e753c9bbb3461dbb10cde2adc2cb12c
Gerrit-Change-Number: 56809
Gerrit-PatchSet: 3
Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-MessageType: merged
Attention is currently required from: Raul Rangel, Nikolai Vyssotski, Rob Barnes, Julian Schroeder.
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57294 )
Change subject: device/dram: Add addtional LPDDR4 speed grades
......................................................................
Patch Set 2:
(2 comments)
File src/device/dram/lpddr4.c:
https://review.coreboot.org/c/coreboot/+/57294/comment/f4a969cc_f562ca11
PS1, Line 51: 934
> Could go either way. JEDEC Standard No. 79-4C / Table 169 says DDR4-1866 tck(avg) min = 1.071ns. […]
ok, since the nominal value should be within the range specified by min_clock_mhz and max_clock_mhz, we should probably go with 934 here to be on the safe side
https://review.coreboot.org/c/coreboot/+/57294/comment/6bc304f1_81164e07
PS1, Line 81: 2137
> JEDEC Standard No. 209-4 Table 88 says LPDDR4-4266 tck(avg) min = 0.467ns. 1/0. […]
2134 sounds correct to me
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Gerrit-Change-Id: Ie7706fd4ad5a7df68c07b8ca43261429ba140c61
Gerrit-Change-Number: 57294
Gerrit-PatchSet: 2
Gerrit-Owner: Rob Barnes <robbarnes(a)google.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
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Gerrit-Reviewer: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com>
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Gerrit-MessageType: comment
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57341 )
Change subject: mb/google/volteer: Move EC_HOST_EVENT_USB_MUX wake event to S0ix only
......................................................................
mb/google/volteer: Move EC_HOST_EVENT_USB_MUX wake event to S0ix only
If a USB_MUX_EVENT happens while the AP is in S3 during powerdown
transtion (S0->S3->S5), this will cause the device to boot again after
it has finished sequencing down to S5. Since S3 is not POR for ChromeOS
devices anymore, change this event to wake from S3 and S0ix to just
S0ix.
BUG=b:197039097
TEST=abuild
Change-Id: I91e5e0ab8301377817875b6fa9e3c0e1f96c1465
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57341
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao(a)google.com>
Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com>
---
M src/mainboard/google/volteer/variants/baseboard/include/baseboard/ec.h
1 file changed, 3 insertions(+), 2 deletions(-)
Approvals:
build bot (Jenkins): Verified
Nick Vaccaro: Looks good to me, approved
Zhuohao Lee: Looks good to me, approved
diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/ec.h
index 253ab68..5ae32fa 100644
--- a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/ec.h
+++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/ec.h
@@ -37,10 +37,11 @@
EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
-#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS)
+#define MAINBOARD_EC_S0IX_WAKE_EVENTS \
+ (MAINBOARD_EC_S3_WAKE_EVENTS |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX))
/* Log EC wake events plus EC shutdown events */
#define MAINBOARD_EC_LOG_EVENTS \
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Gerrit-Change-Number: 57341
Gerrit-PatchSet: 2
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Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
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Gerrit-MessageType: merged