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Change subject: mb/**/gma-mainboard.ads: Use lowercase for `others`
......................................................................
Patch Set 1: Code-Review+2
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Change subject: device/device.h: Drop unused function declaration
......................................................................
Patch Set 1: Code-Review+2
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Change subject: mb/**/gma-mainboard.ads: Use lowercase for `others`
......................................................................
mb/**/gma-mainboard.ads: Use lowercase for `others`
These two files are the only places where the `others` keyword is
capitalised. Use lowercase for consistency with the rest of the tree.
Change-Id: I6b785e28d1d00a11b802a44348a7132ceb6b599d
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/mainboard/51nb/x210/gma-mainboard.ads
M src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/gma-mainboard.ads
2 files changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/57399/1
diff --git a/src/mainboard/51nb/x210/gma-mainboard.ads b/src/mainboard/51nb/x210/gma-mainboard.ads
index 6fb2080..d65c25d 100644
--- a/src/mainboard/51nb/x210/gma-mainboard.ads
+++ b/src/mainboard/51nb/x210/gma-mainboard.ads
@@ -12,6 +12,6 @@
(DP1,
DP2,
eDP,
- Others => Disabled);
+ others => Disabled);
end GMA.Mainboard;
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/gma-mainboard.ads b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/gma-mainboard.ads
index aa8a70d..b5bfff1 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/gma-mainboard.ads
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/gma-mainboard.ads
@@ -11,6 +11,6 @@
ports : constant Port_List :=
(HDMI3,
Analog,
- Others => Disabled);
+ others => Disabled);
end GMA.Mainboard;
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Change subject: skylake DDR4 boards: Set `CaVrefConfig` to 2
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/kontron/bsl6/romstage.c:
https://review.coreboot.org/c/coreboot/+/57262/comment/7d266e6b_3e4e0090
PS3, Line 40: memory_params->CaVrefConfig = 2;
> If you have schematics, it's very easy to check what the correct value is.
I know ;) s/have/had/
> I wrote a very long comment in CB:52110 that should explain what to look for.
>
> With `CaVrefConfig` set to 0 on DDR4, MRC still adjusts write Vref correctly, but sometimes skips configuring CA (Command/Address) Vref for channel 1. I didn't observe any significant differences in my tests on 1DPC (DPC = DIMM Per Channel) configurations, as CA margins are pretty large. However, there could be issues with 2DPC configurations (margins aren't as good).
>
> TL;DR: I don't expect this change to make any noticeable difference, especially on this particular board.
Ack, it's 1DPC anyway.
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Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/57398 )
Change subject: device/device.h: Drop unused function declaration
......................................................................
device/device.h: Drop unused function declaration
The `dev_optimize()` function is neither defined nor used anywhere in
the tree. Drop its unnecessary declaration.
Change-Id: I902bda3244c6496a04f364fad3ecbbdd118dd543
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/include/device/device.h
1 file changed, 0 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/57398/1
diff --git a/src/include/device/device.h b/src/include/device/device.h
index 8f0650f..5a9b9e5 100644
--- a/src/include/device/device.h
+++ b/src/include/device/device.h
@@ -175,7 +175,6 @@
void dev_configure(void);
void dev_enable(void);
void dev_initialize(void);
-void dev_optimize(void);
void dev_finalize(void);
void dev_finalize_chips(void);
/* Function used to override device state */
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Change subject: utils/abuild: select FSP_USE_REPO instead of ADD_FSP_BINARIES
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
Patchset:
PS2:
So, if I understand this right, it only worked because for platforms
without public binaries the paths of the files to add were empty?
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Change subject: soc/intel/alderlake: Clear RTC_BATTERY_DEAD
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/alderlake/pmutil.c:
https://review.coreboot.org/c/coreboot/+/56617/comment/d8d8a9cb_d01dd6c2
PS1, Line 188: soc_get_rtc_failed
> This series looks okay to me. I am wondering if there is scope for us to simplify things somewhat. […]
Handling RTC failures in bootblock sounds like a good idea, especially considering that some CMOS options are read in bootblock and/or romstage.
Looks like this is also what Intel suggests doing. Document 549921 (SKL/KBL PCH BS) section 5.11 (Platform Controller Hub (PCH) Boot Checklist) lists checking the RTC Battery failure bit before programming I/O base addresses (ABASE, TCOBASE) and before disabling the watchdog timer reset.
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57333 )
Change subject: Rename MMCONF Kconfigs to ECAM_MMCONF
......................................................................
Patch Set 5:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/57333/comment/ca635a53_a113b593
PS4, Line 9: the MMCONF Kconfigs only use the Enhanced Configuration
: Access mechanism (ECAM) method
> Reading following two docs again: […]
The IO/MMIO distinction seems x86 specific to me, where we have two
mechanisms concurrently. I'd say all other platforms simply need to
implement some PCI OPS, without any special notion. They can use
`device/pci_mmio_ops.h` for this, but don't have to.
Patchset:
PS5:
Can we please back up a little and discuss this on the mailing list first?
I've skimmed through the comments and it seems there is a lot of confusion
both for authors and reviewers what is architecture specific and what isn't.
And so far I see no reasoning about requirements; it looks like this patch
is just growing in uncontrolled directions.
I'd like to start with some simple questions, e.g.
* Does QC actually call their mechanism MMCONF(IG)?
* Does any other project use the MMCONF term for more than coreboot currently does?
* What does/should the term MMCONF comprise? Isn't it it about (directly) memory mapping PCI(e) config space? which QC doesn't do, as it seems
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Change subject: soc/intel/alderlake: Clear RTC_BATTERY_DEAD
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/alderlake/pmutil.c:
https://review.coreboot.org/c/coreboot/+/56617/comment/edd2c212_baa5c399
PS1, Line 188: soc_get_rtc_failed
> Done
This series looks okay to me. I am wondering if there is scope for us to simplify things somewhat.
Currently, there are two paths in coreboot:
1. verstage: Checks if CMOS failed (and clears failed flag). If yes, then it calls cmos_init.
2. ramstage: Checks if CMOS failed (and clears failed flag). If yes, then it calls cmos_check_update_date and cmos_init.
Should this instead be such that:
1. bootblock checks for CMOS failed and takes all appropriate steps to fix that and clears RTC failed flag.
2. verstage wouldn't check for CMOS failure at all. Instead it has its own checksum that it does to see if VBNV contents are valid. If not, it restores from backup (This checksum and restore is already done in `read_vbnv_cmos()`.
3. ramstage doesn't need to do anything special.
With this, bootblock always inits CMOS correctly and this doesn't need to be handled in different stages. Thoughts?
(Also, the same needs to be aligned on AMD platforms as well).
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