coreboot-gerrit September 2021

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Change in coreboot[master]: HACK: Herobrine: Reinit TPM INT gpio after qclib executes
by build bot (Jenkins) (Code Review) 07 Sep '21

07 Sep '21

Attention is currently required from: Ravi kumar, Shelley Chen, mturney mturney. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57025 ) Change subject: HACK: Herobrine: Reinit TPM INT gpio after qclib executes ...................................................................... Patch Set 5: Verified-1 (2 comments) File src/soc/qualcomm/common/qclib.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-127622): https://review.coreboot.org/c/coreboot/+/57025/comment/94aeab6a_1f952539 PS5, Line 220: mainboard_blob_fix(); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-127622): https://review.coreboot.org/c/coreboot/+/57025/comment/0db2a46e_996efb6d PS5, Line 220: mainboard_blob_fix(); please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/57025 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c43d120ebb49800c82aec263ff8c215b60c5201 Gerrit-Change-Number: 57025 Gerrit-PatchSet: 5 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Comment-Date: Tue, 07 Sep 2021 11:59:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: HACK: Herobrine: Reinit TPM INT GPIO
by build bot (Jenkins) (Code Review) 07 Sep '21

07 Sep '21

Attention is currently required from: Ravi kumar, Shelley Chen, mturney mturney. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57022 ) Change subject: HACK: Herobrine: Reinit TPM INT GPIO ...................................................................... Patch Set 5: Verified-1 (2 comments) File src/mainboard/google/herobrine/mainboard.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-127621): https://review.coreboot.org/c/coreboot/+/57022/comment/1207f590_543cfed9 PS5, Line 53: mainboard_blob_fix(); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-127621): https://review.coreboot.org/c/coreboot/+/57022/comment/fe1446d3_542a8a11 PS5, Line 53: mainboard_blob_fix(); please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/57022 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30426cc0392a640fb6d3b1d0fafca7e9a67a76c3 Gerrit-Change-Number: 57022 Gerrit-PatchSet: 5 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Comment-Date: Tue, 07 Sep 2021 11:59:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: HACK sc7280: QSIP SPI NOR addressing mode for SKU1 and SKU2 HACK
by build bot (Jenkins) (Code Review) 07 Sep '21

07 Sep '21

Attention is currently required from: Shelley Chen, Ravi kumar, Sudheer Amrabadi, mturney mturney. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50586 ) Change subject: HACK sc7280: QSIP SPI NOR addressing mode for SKU1 and SKU2 HACK ...................................................................... Patch Set 68: Verified-1 (2 comments) File src/drivers/spi/spi_flash.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-127618): https://review.coreboot.org/c/coreboot/+/50586/comment/ce17ec71_1cbb88ad PS68, Line 533: while (1) suspect code indent for conditional statements (24, 24) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-127618): https://review.coreboot.org/c/coreboot/+/50586/comment/1e6eb5c6_ca8444c0 PS68, Line 554: while (1) suspect code indent for conditional statements (24, 24) -- To view, visit https://review.coreboot.org/c/coreboot/+/50586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied5b647d0fcc8e3effff3bb7c8680ed5a0c1f3d4 Gerrit-Change-Number: 50586 Gerrit-PatchSet: 68 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Sajida Bhanu <sbhanu(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Comment-Date: Tue, 07 Sep 2021 11:58:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: sc7280: Add PCIe RC driver in Coreboot
by build bot (Jenkins) (Code Review) 07 Sep '21

07 Sep '21

Attention is currently required from: Shelley Chen, Ravi kumar, Furquan Shaikh, Sudheer Amrabadi, Julius Werner, mturney mturney. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53902 ) Change subject: sc7280: Add PCIe RC driver in Coreboot ...................................................................... Patch Set 35: Verified-1 (1 comment) File src/soc/qualcomm/sc7280/include/soc/pcie.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-127613): https://review.coreboot.org/c/coreboot/+/53902/comment/2d421170_e120cba5 PS35, Line 168: #define PCIE_DEV_FUNC (dev, func) {(PCI_SLOT(devfn)) | (PCI_FUNC(devfn))} Macros with complex values should be enclosed in parentheses -- To view, visit https://review.coreboot.org/c/coreboot/+/53902 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccf60aa56541f5230fa9c3f821d7709615c36631 Gerrit-Change-Number: 53902 Gerrit-PatchSet: 35 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Prasad Malisetty <pmaliset(a)qualcomm.corp-partner.google.com> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Comment-Date: Tue, 07 Sep 2021 11:57:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/tsc: Deduplicate Makefile logic
by Angel Pons (Code Review) 07 Sep '21

07 Sep '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/57456 ) Change subject: cpu/x86/tsc: Deduplicate Makefile logic ...................................................................... cpu/x86/tsc: Deduplicate Makefile logic The code under `cpu/x86/tsc` is only compiled in when its `Makefile.inc` is included from platform (CPU/SoC) code and the `UDELAY_TSC` Kconfig option is enabled. Include `cpu/x86/tsc/Makefile.inc` once from `cpu/x86/Makefile.inc` and drop the now-redundant inclusions from platform code. Also, deduplicate the `UDELAY_TSC` guards. Change-Id: I41e96026f37f19de954fd5985b92a08cb97876c1 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/amd/agesa/family14/Makefile.inc M src/cpu/amd/agesa/family15tn/Makefile.inc M src/cpu/amd/agesa/family16kb/Makefile.inc M src/cpu/amd/pi/00730F01/Makefile.inc M src/cpu/intel/haswell/Makefile.inc M src/cpu/intel/model_2065x/Makefile.inc M src/cpu/intel/model_206ax/Makefile.inc M src/cpu/intel/slot_1/Makefile.inc M src/cpu/intel/socket_441/Makefile.inc M src/cpu/intel/socket_BGA956/Makefile.inc M src/cpu/intel/socket_FCBGA559/Makefile.inc M src/cpu/intel/socket_LGA775/Makefile.inc M src/cpu/intel/socket_m/Makefile.inc M src/cpu/intel/socket_mPGA604/Makefile.inc M src/cpu/intel/socket_p/Makefile.inc M src/cpu/qemu-x86/Makefile.inc M src/cpu/x86/Makefile.inc M src/cpu/x86/tsc/Makefile.inc M src/soc/amd/common/block/cpu/tsc/Makefile.inc M src/soc/amd/stoneyridge/Makefile.inc M src/soc/intel/alderlake/Makefile.inc M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/baytrail/Makefile.inc M src/soc/intel/braswell/Makefile.inc M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/denverton_ns/Makefile.inc M src/soc/intel/elkhartlake/Makefile.inc M src/soc/intel/icelake/Makefile.inc M src/soc/intel/jasperlake/Makefile.inc M src/soc/intel/quark/Makefile.inc M src/soc/intel/skylake/Makefile.inc M src/soc/intel/tigerlake/Makefile.inc M src/soc/intel/xeon_sp/cpx/Makefile.inc M src/soc/intel/xeon_sp/skx/Makefile.inc 34 files changed, 7 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/57456/1 diff --git a/src/cpu/amd/agesa/family14/Makefile.inc b/src/cpu/amd/agesa/family14/Makefile.inc index e73e8dd..c9074d87 100644 --- a/src/cpu/amd/agesa/family14/Makefile.inc +++ b/src/cpu/amd/agesa/family14/Makefile.inc @@ -7,7 +7,6 @@ ramstage-y += model_14_init.c subdirs-y += ../../mtrr -subdirs-y += ../../../x86/tsc subdirs-y += ../../../x86/lapic subdirs-y += ../../../x86/cache subdirs-y += ../../../x86/mtrr diff --git a/src/cpu/amd/agesa/family15tn/Makefile.inc b/src/cpu/amd/agesa/family15tn/Makefile.inc index b2225b8..42e1c2c 100644 --- a/src/cpu/amd/agesa/family15tn/Makefile.inc +++ b/src/cpu/amd/agesa/family15tn/Makefile.inc @@ -10,7 +10,6 @@ subdirs-y += ../../mtrr subdirs-y += ../../smm -subdirs-y += ../../../x86/tsc subdirs-y += ../../../x86/lapic subdirs-y += ../../../x86/cache subdirs-y += ../../../x86/mtrr diff --git a/src/cpu/amd/agesa/family16kb/Makefile.inc b/src/cpu/amd/agesa/family16kb/Makefile.inc index 6f5d439..05e61ea 100644 --- a/src/cpu/amd/agesa/family16kb/Makefile.inc +++ b/src/cpu/amd/agesa/family16kb/Makefile.inc @@ -7,7 +7,6 @@ ramstage-y += model_16_init.c subdirs-y += ../../mtrr -subdirs-y += ../../../x86/tsc subdirs-y += ../../../x86/lapic subdirs-y += ../../../x86/cache subdirs-y += ../../../x86/mtrr diff --git a/src/cpu/amd/pi/00730F01/Makefile.inc b/src/cpu/amd/pi/00730F01/Makefile.inc index ae2db0f..446be5d 100644 --- a/src/cpu/amd/pi/00730F01/Makefile.inc +++ b/src/cpu/amd/pi/00730F01/Makefile.inc @@ -8,7 +8,6 @@ ramstage-y += update_microcode.c subdirs-y += ../../mtrr -subdirs-y += ../../../x86/tsc subdirs-y += ../../../x86/lapic subdirs-y += ../../../x86/cache subdirs-y += ../../../x86/mtrr diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index bc624f7..ebdcc91 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -15,7 +15,6 @@ postcar-y += ../car/non-evict/exit_car.S -subdirs-y += ../../x86/tsc subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/lapic subdirs-y += ../../x86/cache diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc index 817e0b7..85602de 100644 --- a/src/cpu/intel/model_2065x/Makefile.inc +++ b/src/cpu/intel/model_2065x/Makefile.inc @@ -3,7 +3,6 @@ subdirs-y += ../../x86/cache subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/lapic -subdirs-y += ../../x86/tsc subdirs-y += ../../intel/turbo subdirs-y += ../../intel/microcode subdirs-y += ../smm/gen1 diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc index 5f39495..2b28eb4f 100644 --- a/src/cpu/intel/model_206ax/Makefile.inc +++ b/src/cpu/intel/model_206ax/Makefile.inc @@ -2,7 +2,6 @@ subdirs-y += ../../x86/name subdirs-y += ../smm/gen1 -subdirs-y += ../../x86/tsc subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/lapic subdirs-y += ../../x86/cache diff --git a/src/cpu/intel/slot_1/Makefile.inc b/src/cpu/intel/slot_1/Makefile.inc index 9044de8..df7a0bd 100644 --- a/src/cpu/intel/slot_1/Makefile.inc +++ b/src/cpu/intel/slot_1/Makefile.inc @@ -7,7 +7,6 @@ subdirs-y += ../model_67x subdirs-y += ../model_68x subdirs-y += ../model_6bx -subdirs-y += ../../x86/tsc subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/lapic subdirs-y += ../../x86/cache diff --git a/src/cpu/intel/socket_441/Makefile.inc b/src/cpu/intel/socket_441/Makefile.inc index 9268def..47fa296 100644 --- a/src/cpu/intel/socket_441/Makefile.inc +++ b/src/cpu/intel/socket_441/Makefile.inc @@ -1,5 +1,4 @@ subdirs-y += ../model_106cx -subdirs-y += ../../x86/tsc subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/lapic subdirs-y += ../../x86/cache diff --git a/src/cpu/intel/socket_BGA956/Makefile.inc b/src/cpu/intel/socket_BGA956/Makefile.inc index 2c18f66..bdf90a9 100644 --- a/src/cpu/intel/socket_BGA956/Makefile.inc +++ b/src/cpu/intel/socket_BGA956/Makefile.inc @@ -1,5 +1,4 @@ subdirs-y += ../model_1067x -subdirs-y += ../../x86/tsc subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/lapic subdirs-y += ../../x86/cache diff --git a/src/cpu/intel/socket_FCBGA559/Makefile.inc b/src/cpu/intel/socket_FCBGA559/Makefile.inc index 7904e17..3a0db36 100644 --- a/src/cpu/intel/socket_FCBGA559/Makefile.inc +++ b/src/cpu/intel/socket_FCBGA559/Makefile.inc @@ -1,5 +1,4 @@ subdirs-y += ../model_106cx -subdirs-y += ../../x86/tsc subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/lapic subdirs-y += ../../x86/cache diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc index 9b571f5..f684bfb 100644 --- a/src/cpu/intel/socket_LGA775/Makefile.inc +++ b/src/cpu/intel/socket_LGA775/Makefile.inc @@ -4,7 +4,6 @@ #subdirs-y += ../model_f6x #subdirs-y += ../model_1066x subdirs-y += ../model_1067x -subdirs-y += ../../x86/tsc subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/lapic subdirs-y += ../../x86/cache diff --git a/src/cpu/intel/socket_m/Makefile.inc b/src/cpu/intel/socket_m/Makefile.inc index 4fd01ac..2192328 100644 --- a/src/cpu/intel/socket_m/Makefile.inc +++ b/src/cpu/intel/socket_m/Makefile.inc @@ -1,6 +1,5 @@ subdirs-y += ../model_6ex subdirs-y += ../model_6fx -subdirs-y += ../../x86/tsc subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/lapic subdirs-y += ../../x86/cache diff --git a/src/cpu/intel/socket_mPGA604/Makefile.inc b/src/cpu/intel/socket_mPGA604/Makefile.inc index 32bb474..345e4e0 100644 --- a/src/cpu/intel/socket_mPGA604/Makefile.inc +++ b/src/cpu/intel/socket_mPGA604/Makefile.inc @@ -1,5 +1,4 @@ subdirs-y += ../model_f2x -subdirs-y += ../../x86/tsc subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/lapic subdirs-y += ../../x86/cache diff --git a/src/cpu/intel/socket_p/Makefile.inc b/src/cpu/intel/socket_p/Makefile.inc index 4156052..2565493 100644 --- a/src/cpu/intel/socket_p/Makefile.inc +++ b/src/cpu/intel/socket_p/Makefile.inc @@ -1,6 +1,5 @@ subdirs-y += ../model_6fx subdirs-y += ../model_1067x -subdirs-y += ../../x86/tsc subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/lapic subdirs-y += ../../x86/cache diff --git a/src/cpu/qemu-x86/Makefile.inc b/src/cpu/qemu-x86/Makefile.inc index a286db9..1b1b603 100644 --- a/src/cpu/qemu-x86/Makefile.inc +++ b/src/cpu/qemu-x86/Makefile.inc @@ -9,4 +9,3 @@ subdirs-y += ../x86/mtrr subdirs-y += ../x86/lapic -subdirs-y += ../x86/tsc diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index 1c62119..1ad04b5 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -1,5 +1,6 @@ subdirs-y += pae subdirs-$(CONFIG_HAVE_SMI_HANDLER) += smm +subdirs-$(CONFIG_UDELAY_TSC) += tsc all-$(CONFIG_ARCH_ALL_STAGES_X86_64) += 64bit/mode_switch.S diff --git a/src/cpu/x86/tsc/Makefile.inc b/src/cpu/x86/tsc/Makefile.inc index a0cd145..978d7fa 100644 --- a/src/cpu/x86/tsc/Makefile.inc +++ b/src/cpu/x86/tsc/Makefile.inc @@ -1,6 +1,6 @@ -bootblock-$(CONFIG_UDELAY_TSC) += delay_tsc.c -ramstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c -romstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c -verstage_x86-$(CONFIG_UDELAY_TSC) += delay_tsc.c -postcar-$(CONFIG_UDELAY_TSC) += delay_tsc.c -smm-$(CONFIG_UDELAY_TSC) += delay_tsc.c +bootblock-y += delay_tsc.c +ramstage-y += delay_tsc.c +romstage-y += delay_tsc.c +verstage_x86-y += delay_tsc.c +postcar-y += delay_tsc.c +smm-y += delay_tsc.c diff --git a/src/soc/amd/common/block/cpu/tsc/Makefile.inc b/src/soc/amd/common/block/cpu/tsc/Makefile.inc index 4f2729b..e24db58 100644 --- a/src/soc/amd/common/block/cpu/tsc/Makefile.inc +++ b/src/soc/amd/common/block/cpu/tsc/Makefile.inc @@ -1,7 +1,5 @@ ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H),y) -subdirs-y += ../../../../../../cpu/x86/tsc - bootblock-y += tsc_freq.c bootblock-y += monotonic_timer.c diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index c3ca69d..fb6e204 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -3,7 +3,6 @@ ifeq ($(CONFIG_SOC_AMD_STONEYRIDGE),y) subdirs-y += ../../../cpu/amd/mtrr/ -subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/cache subdirs-y += ../../../cpu/x86/mtrr diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc index 783a445..c7e0abc 100644 --- a/src/soc/intel/alderlake/Makefile.inc +++ b/src/soc/intel/alderlake/Makefile.inc @@ -4,7 +4,6 @@ subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr -subdirs-y += ../../../cpu/x86/tsc # all (bootblock, verstage, romstage, postcar, ramstage) all-y += gspi.c diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 778811e..49707da 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -5,7 +5,6 @@ subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr -subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/x86/cache bootblock-y += bootblock/bootblock.c diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index f4c4d7e..1fabd4f 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -3,7 +3,6 @@ subdirs-y += romstage subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr -subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/intel/common diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index dade9a2..0080d72 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -3,7 +3,6 @@ subdirs-y += romstage subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr -subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/intel/common diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 2da8921..49e9f0c 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -5,7 +5,6 @@ subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr -subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/intel/common bootblock-y += bootblock/bootblock.c diff --git a/src/soc/intel/denverton_ns/Makefile.inc b/src/soc/intel/denverton_ns/Makefile.inc index beb3471..c222920 100644 --- a/src/soc/intel/denverton_ns/Makefile.inc +++ b/src/soc/intel/denverton_ns/Makefile.inc @@ -6,7 +6,6 @@ subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr -subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/x86/cache bootblock-y += bootblock/bootblock.c diff --git a/src/soc/intel/elkhartlake/Makefile.inc b/src/soc/intel/elkhartlake/Makefile.inc index 462bc3a..e3cf119 100644 --- a/src/soc/intel/elkhartlake/Makefile.inc +++ b/src/soc/intel/elkhartlake/Makefile.inc @@ -5,7 +5,6 @@ subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr -subdirs-y += ../../../cpu/x86/tsc # all (bootblock, verstage, romstage, postcar, ramstage) all-y += gspi.c diff --git a/src/soc/intel/icelake/Makefile.inc b/src/soc/intel/icelake/Makefile.inc index c16195f..a53a225 100644 --- a/src/soc/intel/icelake/Makefile.inc +++ b/src/soc/intel/icelake/Makefile.inc @@ -5,7 +5,6 @@ subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr -subdirs-y += ../../../cpu/x86/tsc # all (bootblock, verstage, romstage, postcar, ramstage) all-y += gspi.c diff --git a/src/soc/intel/jasperlake/Makefile.inc b/src/soc/intel/jasperlake/Makefile.inc index 56aad1f..f450257 100644 --- a/src/soc/intel/jasperlake/Makefile.inc +++ b/src/soc/intel/jasperlake/Makefile.inc @@ -5,7 +5,6 @@ subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr -subdirs-y += ../../../cpu/x86/tsc # all (bootblock, verstage, romstage, postcar, ramstage) all-y += gspi.c diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index 387884a..c0b213e 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -4,7 +4,6 @@ subdirs-y += romstage subdirs-y += ../../../cpu/x86/mtrr -subdirs-y += ../../../cpu/x86/tsc bootblock-y += bootblock/esram_init.S bootblock-y += bootblock/bootblock.c diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 0e9d6f9..c191aac 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -7,7 +7,6 @@ subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr -subdirs-y += ../../../cpu/x86/tsc bootblock-y += bootblock/bootblock.c bootblock-y += i2c.c diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index b50047e..0ec8e84 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -5,7 +5,6 @@ subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr -subdirs-y += ../../../cpu/x86/tsc # all (bootblock, verstage, romstage, postcar, ramstage) all-y += gspi.c diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.inc b/src/soc/intel/xeon_sp/cpx/Makefile.inc index b2e653e..4d494b5 100644 --- a/src/soc/intel/xeon_sp/cpx/Makefile.inc +++ b/src/soc/intel/xeon_sp/cpx/Makefile.inc @@ -5,7 +5,6 @@ subdirs-y += ../../../../cpu/intel/turbo subdirs-y += ../../../../cpu/x86/lapic subdirs-y += ../../../../cpu/x86/mtrr -subdirs-y += ../../../../cpu/x86/tsc subdirs-y += ../../../../cpu/intel/microcode romstage-y += romstage.c ddr.c diff --git a/src/soc/intel/xeon_sp/skx/Makefile.inc b/src/soc/intel/xeon_sp/skx/Makefile.inc index 7663602..5840580 100644 --- a/src/soc/intel/xeon_sp/skx/Makefile.inc +++ b/src/soc/intel/xeon_sp/skx/Makefile.inc @@ -6,7 +6,6 @@ subdirs-y += ../../../../cpu/intel/turbo subdirs-y += ../../../../cpu/x86/lapic subdirs-y += ../../../../cpu/x86/mtrr -subdirs-y += ../../../../cpu/x86/tsc subdirs-y += ../../../../cpu/x86/cache postcar-y += soc_util.c -- To view, visit https://review.coreboot.org/c/coreboot/+/57456 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41e96026f37f19de954fd5985b92a08cb97876c1 Gerrit-Change-Number: 57456 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mainboard/google: Update the TLMM registers for sdhc
by Ravi kumar (Code Review) 07 Sep '21

07 Sep '21

Attention is currently required from: Sajida Bhanu. Hello Sajida Bhanu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/57450 to review the following change. Change subject: mainboard/google: Update the TLMM registers for sdhc ...................................................................... mainboard/google: Update the TLMM registers for sdhc Update the TLMM register values for eMMC and SD card on Trogdor, Herobrine and Mistral boards. BUG=b:196936525 TEST=Validated on qualcomm sc7280 and sc7180 development board and checked basic boot up. Signed-off-by: Shaik Sajida Bhanu <sbhanu(a)codeaurora.org> Change-Id: Iccdb7757027c6de424a82e4374bad802501ac83c --- M src/mainboard/google/herobrine/mainboard.c M src/mainboard/google/mistral/mainboard.c M src/mainboard/google/trogdor/mainboard.c M src/soc/qualcomm/qcs405/include/soc/addressmap.h M src/soc/qualcomm/sc7180/include/soc/addressmap.h M src/soc/qualcomm/sc7280/include/soc/addressmap.h 6 files changed, 39 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/57450/1 diff --git a/src/mainboard/google/herobrine/mainboard.c b/src/mainboard/google/herobrine/mainboard.c index e4ea344..246f710 100644 --- a/src/mainboard/google/herobrine/mainboard.c +++ b/src/mainboard/google/herobrine/mainboard.c @@ -12,6 +12,7 @@ #include <soc/usb/usb_common.h> #include <delay.h> #include <soc/pcie.h> +#include <soc/addressmap.h> static void setup_pcie(void) { @@ -62,12 +63,21 @@ GPIO_NO_PULL, GPIO_16MA, GPIO_OUTPUT); } +static void configure_sdhci(void) +{ + /*Update TLMM Register for eMMC*/ + write32((void *)SDC1_TLMM_CFG_ADDR, 0x9FE4); + /*Update TLMM Register for SD card*/ + write32((void *)SDC2_TLMM_CFG_ADDR, 0x1FE4); +} + static void mainboard_init(struct device *dev) { /* Configure clock for eMMC */ clock_configure_sdcc(1, 384 * MHz); /* Configure clock for SD card */ clock_configure_sdcc(2, 50 * MHz); + configure_sdhci(); gpi_firmware_load(QUP_0_GSI_BASE); gpi_firmware_load(QUP_1_GSI_BASE); diff --git a/src/mainboard/google/mistral/mainboard.c b/src/mainboard/google/mistral/mainboard.c index 804afb4..3b5c804 100644 --- a/src/mainboard/google/mistral/mainboard.c +++ b/src/mainboard/google/mistral/mainboard.c @@ -3,6 +3,7 @@ #include <device/device.h> #include <vendorcode/google/chromeos/chromeos.h> #include <soc/usb.h> +#include <soc/addressmap.h> static struct usb_board_data usb1_board_data = { .parameter_override_x0 = 0x63, @@ -17,6 +18,12 @@ setup_usb_host(HSUSB_HS_PORT_1, &usb1_board_data); } +static void configure_sdhci(void) +{ + /*Update TLMM Register for eMMC*/ + write32((void *)SDC1_TLMM_CFG_ADDR, 0x9FE4); +} + static void mainboard_init(struct device *dev) { /* Copy WIFI calibration data into CBMEM. */ @@ -24,6 +31,7 @@ cbmem_add_vpd_calibration_data(); setup_usb(); + configure_sdhci(); } static void mainboard_enable(struct device *dev) diff --git a/src/mainboard/google/trogdor/mainboard.c b/src/mainboard/google/trogdor/mainboard.c index b55c75f..f68cf2a 100644 --- a/src/mainboard/google/trogdor/mainboard.c +++ b/src/mainboard/google/trogdor/mainboard.c @@ -18,6 +18,7 @@ #include <soc/qcom_qup_se.h> #include <soc/usb/usb_common.h> #include "board.h" +#include <soc/addressmap.h> #define BRIDGE_BUS 0x2 #define BRIDGE_CHIP 0x2d @@ -145,6 +146,14 @@ fb_new_framebuffer_info_from_edid(&panel->edid, 0); } +static void configure_sdhci(void) +{ + /*Update TLMM Register for eMMC*/ + write32((void *)SDC1_TLMM_CFG_ADDR, 0x9FFF); + /*Update TLMM Register for SD card*/ + write32((void *)SDC2_TLMM_CFG_ADDR, 0x1FE4); +} + static void mainboard_init(struct device *dev) { /* Take FPMCU out of reset. Power was already applied @@ -156,6 +165,7 @@ qi2s_configure_gpios(); load_qup_fw(); display_startup(); + configure_sdhci(); } static void mainboard_enable(struct device *dev) diff --git a/src/soc/qualcomm/qcs405/include/soc/addressmap.h b/src/soc/qualcomm/qcs405/include/soc/addressmap.h index b21ae26..6d602eb 100644 --- a/src/soc/qualcomm/qcs405/include/soc/addressmap.h +++ b/src/soc/qualcomm/qcs405/include/soc/addressmap.h @@ -9,4 +9,7 @@ #define TLMM_SOUTH_TILE_BASE 0x1000000 #define GCC_BASE 0x01800000 +/*SDHC TLMM Registers */ +#define SDC1_TLMM_CFG_ADDR 0x010C2000 + #endif /* __SOC_QUALCOMM_QCS405_ADDRESS_MAP_H__ */ diff --git a/src/soc/qualcomm/sc7180/include/soc/addressmap.h b/src/soc/qualcomm/sc7180/include/soc/addressmap.h index e360e8a..a2a4461 100644 --- a/src/soc/qualcomm/sc7180/include/soc/addressmap.h +++ b/src/soc/qualcomm/sc7180/include/soc/addressmap.h @@ -56,4 +56,8 @@ #define GPIO_FUNC_QSPI_DATA_1 GPIO65_FUNC_QSPI_DATA_1 #define GPIO_FUNC_QSPI_CLK GPIO63_FUNC_QSPI_CLK +/*SDHC TLMM Registers */ +#define SDC1_TLMM_CFG_ADDR 0x03D7A000 +#define SDC2_TLMM_CFG_ADDR 0x03D7B000 + #endif /* __SOC_QUALCOMM_SC7180_ADDRESS_MAP_H__ */ diff --git a/src/soc/qualcomm/sc7280/include/soc/addressmap.h b/src/soc/qualcomm/sc7280/include/soc/addressmap.h index b15765f..4f7c398 100644 --- a/src/soc/qualcomm/sc7280/include/soc/addressmap.h +++ b/src/soc/qualcomm/sc7280/include/soc/addressmap.h @@ -93,4 +93,8 @@ /*PHY BCR */ #define GCC_PCIE_1_PHY_BCR 0x18E01C +/*SDHC TLMM Registers */ +#define SDC1_TLMM_CFG_ADDR 0x0F1B3000 +#define SDC2_TLMM_CFG_ADDR 0x0F1B4000 + #endif /* __SOC_QUALCOMM_SC7280_ADDRESS_MAP_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/57450 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccdb7757027c6de424a82e4374bad802501ac83c Gerrit-Change-Number: 57450 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Sajida Bhanu <sbhanu(a)codeaurora.org> Gerrit-Attention: Sajida Bhanu <sbhanu(a)codeaurora.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: Herobrine: sc7280: Add support for audio
by Ravi kumar (Code Review) 07 Sep '21

07 Sep '21

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/57449 ) Change subject: Herobrine: sc7280: Add support for audio ...................................................................... Herobrine: sc7280: Add support for audio Add gpio configuration for target specific i2s ports BUG=b:182963902 TEST=Validated on qualcomm sc7280 developement board Signed-off-by: Srinivasa Rao Mandadapu <srivasam(a)codeaurora.org> Change-Id: I2ce95332f892d5d4acb2755307df84d37feb8002 --- M src/mainboard/google/herobrine/board.h M src/mainboard/google/herobrine/chromeos.c M src/mainboard/google/herobrine/mainboard.c 3 files changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/57449/1 diff --git a/src/mainboard/google/herobrine/board.h b/src/mainboard/google/herobrine/board.h index c437651..9ca14a3 100644 --- a/src/mainboard/google/herobrine/board.h +++ b/src/mainboard/google/herobrine/board.h @@ -20,6 +20,7 @@ #define GPIO_SD_CD_L GPIO(91) +#define GPIO_AMP_ENABLE GPIO(63) #define QCOM_SC7280_SKU1 0x0 #define QCOM_SC7280_SKU2 0x1 #define QCOM_SC7280_SKU3 0x3 diff --git a/src/mainboard/google/herobrine/chromeos.c b/src/mainboard/google/herobrine/chromeos.c index 6237f4f..6857d6e 100644 --- a/src/mainboard/google/herobrine/chromeos.c +++ b/src/mainboard/google/herobrine/chromeos.c @@ -11,6 +11,7 @@ gpio_input_pullup(GPIO_AP_EC_INT); gpio_input_pullup(GPIO_SD_CD_L); gpio_input_irq(GPIO_H1_AP_INT, IRQ_TYPE_RISING_EDGE, GPIO_PULL_UP); + gpio_output(GPIO_AMP_ENABLE, 0); } void fill_lb_gpios(struct lb_gpios *gpios) @@ -24,6 +25,8 @@ "SD card detect"}, {GPIO_H1_AP_INT.addr, ACTIVE_HIGH, gpio_get(GPIO_H1_AP_INT), "TPM interrupt"}, + {GPIO_AMP_ENABLE.addr, ACTIVE_HIGH, gpio_get(GPIO_AMP_ENABLE), + "speaker enable"}, }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); diff --git a/src/mainboard/google/herobrine/mainboard.c b/src/mainboard/google/herobrine/mainboard.c index c1c2a57..e4ea344 100644 --- a/src/mainboard/google/herobrine/mainboard.c +++ b/src/mainboard/google/herobrine/mainboard.c @@ -49,6 +49,19 @@ setup_usb_host0(); } +static void qi2s_configure_gpios(void) +{ + + gpio_configure(GPIO(106), GPIO106_FUNC_MI2S1_SCK, + GPIO_NO_PULL, GPIO_16MA, GPIO_OUTPUT); + + gpio_configure(GPIO(108), GPIO108_FUNC_MI2S1_WS, + GPIO_NO_PULL, GPIO_16MA, GPIO_OUTPUT); + + gpio_configure(GPIO(107), GPIO107_FUNC_MI2S1_DATA0, + GPIO_NO_PULL, GPIO_16MA, GPIO_OUTPUT); +} + static void mainboard_init(struct device *dev) { /* Configure clock for eMMC */ @@ -82,6 +95,7 @@ setup_usb(); /* Set up PCIe in RC mode */ setup_pcie(); + qi2s_configure_gpios(); } static void mainboard_enable(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/57449 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ce95332f892d5d4acb2755307df84d37feb8002 Gerrit-Change-Number: 57449 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: qualcomm/sc7280: Cleanup common clock driver for sc7280
by Ravi kumar (Code Review) 07 Sep '21

07 Sep '21

Attention is currently required from: Taniya Das. Hello Taniya Das, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/57448 to review the following change. Change subject: qualcomm/sc7280: Cleanup common clock driver for sc7280 ...................................................................... qualcomm/sc7280: Cleanup common clock driver for sc7280 Add support for Zonda PLL enable for CPU in common clock driver. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Taniya Das <tdas(a)codeaurora.org> Change-Id: I795e6cf33ee98204c40ebfafa990be2c24667157 --- M src/soc/qualcomm/common/clock.c M src/soc/qualcomm/common/include/soc/clock_common.h M src/soc/qualcomm/sc7280/clock.c 3 files changed, 26 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/57448/1 diff --git a/src/soc/qualcomm/common/clock.c b/src/soc/qualcomm/common/clock.c index e83f979..09cd95c 100644 --- a/src/soc/qualcomm/common/clock.c +++ b/src/soc/qualcomm/common/clock.c @@ -236,6 +236,29 @@ return CB_SUCCESS; } +enum cb_err zonda_pll_enable(struct alpha_pll_reg_val_config *cfg) +{ + setbits32(cfg->reg_mode, BIT(PLL_BYPASSNL_SHFT)); + + /* + * H/W requires a 1us delay between disabling the bypass and + * de-asserting the reset. + */ + udelay(1); + setbits32(cfg->reg_mode, BIT(PLL_RESET_SHFT)); + setbits32(cfg->reg_opmode, PLL_RUN_MODE); + + if (!wait_us(100, read32(cfg->reg_mode) & PLL_LOCK_DET_BMSK)) { + printk(BIOS_ERR, "ERROR: CPU PLL did not lock!\n"); + return CB_ERR; + } + + setbits32(cfg->reg_user_ctl, PLL_USERCTL_BMSK); + setbits32(cfg->reg_mode, BIT(PLL_OUTCTRL_SHFT)); + + return CB_SUCCESS; +} + /* Bring subsystem out of RESET */ void clock_reset_subsystem(u32 *misc, u32 shft) { diff --git a/src/soc/qualcomm/common/include/soc/clock_common.h b/src/soc/qualcomm/common/include/soc/clock_common.h index b924194..0911827 100644 --- a/src/soc/qualcomm/common/include/soc/clock_common.h +++ b/src/soc/qualcomm/common/include/soc/clock_common.h @@ -155,6 +155,8 @@ bool enable, int br_enable); enum cb_err agera_pll_enable(struct alpha_pll_reg_val_config *cfg); +enum cb_err zonda_pll_enable(struct alpha_pll_reg_val_config *cfg); + struct aoss { u8 _res0[0x50020]; u32 aoss_cc_reset_status; diff --git a/src/soc/qualcomm/sc7280/clock.c b/src/soc/qualcomm/sc7280/clock.c index 871fb9b..07a575b 100644 --- a/src/soc/qualcomm/sc7280/clock.c +++ b/src/soc/qualcomm/sc7280/clock.c @@ -255,7 +255,6 @@ clock_enable(&gcc->qspi_core_cbcr); } - void clock_enable_qup(int qup) { struct qupv3_clock *qup_clk; @@ -412,7 +411,7 @@ if (clk_type >= MDSS_CLK_COUNT) return CB_ERR; - /* Enable clock*/ + /* Enable clock */ return clock_enable(mdss_cbcr[clk_type]); } -- To view, visit https://review.coreboot.org/c/coreboot/+/57448 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I795e6cf33ee98204c40ebfafa990be2c24667157 Gerrit-Change-Number: 57448 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Taniya Das <tdas(a)codeaurora.org> Gerrit-Attention: Taniya Das <tdas(a)codeaurora.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/qualcomm/common: clock: Cleanup common clock driver
by Ravi kumar (Code Review) 07 Sep '21

07 Sep '21

Attention is currently required from: Taniya Das. Hello Taniya Das, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/57447 to review the following change. Change subject: soc/qualcomm/common: clock: Cleanup common clock driver ...................................................................... soc/qualcomm/common: clock: Cleanup common clock driver The common clock driver exposes PLL configuration functions and also different Agera PLL enable functions for the CPU PLLs. BUG=b:182963902 TEST=Validated on qualcomm sc7180 and sc7280 development board. Signed-off-by: Taniya Das <tdas(a)codeaurora.org> Change-Id: Ifabe0508a37a841779965f4e38172f680e18d38a --- M src/soc/qualcomm/common/clock.c M src/soc/qualcomm/common/include/soc/clock_common.h M src/soc/qualcomm/sc7180/clock.c 3 files changed, 3 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/57447/1 diff --git a/src/soc/qualcomm/common/clock.c b/src/soc/qualcomm/common/clock.c index 09cd95c..e83f979 100644 --- a/src/soc/qualcomm/common/clock.c +++ b/src/soc/qualcomm/common/clock.c @@ -236,29 +236,6 @@ return CB_SUCCESS; } -enum cb_err zonda_pll_enable(struct alpha_pll_reg_val_config *cfg) -{ - setbits32(cfg->reg_mode, BIT(PLL_BYPASSNL_SHFT)); - - /* - * H/W requires a 1us delay between disabling the bypass and - * de-asserting the reset. - */ - udelay(1); - setbits32(cfg->reg_mode, BIT(PLL_RESET_SHFT)); - setbits32(cfg->reg_opmode, PLL_RUN_MODE); - - if (!wait_us(100, read32(cfg->reg_mode) & PLL_LOCK_DET_BMSK)) { - printk(BIOS_ERR, "ERROR: CPU PLL did not lock!\n"); - return CB_ERR; - } - - setbits32(cfg->reg_user_ctl, PLL_USERCTL_BMSK); - setbits32(cfg->reg_mode, BIT(PLL_OUTCTRL_SHFT)); - - return CB_SUCCESS; -} - /* Bring subsystem out of RESET */ void clock_reset_subsystem(u32 *misc, u32 shft) { diff --git a/src/soc/qualcomm/common/include/soc/clock_common.h b/src/soc/qualcomm/common/include/soc/clock_common.h index 0911827..b924194 100644 --- a/src/soc/qualcomm/common/include/soc/clock_common.h +++ b/src/soc/qualcomm/common/include/soc/clock_common.h @@ -155,8 +155,6 @@ bool enable, int br_enable); enum cb_err agera_pll_enable(struct alpha_pll_reg_val_config *cfg); -enum cb_err zonda_pll_enable(struct alpha_pll_reg_val_config *cfg); - struct aoss { u8 _res0[0x50020]; u32 aoss_cc_reset_status; diff --git a/src/soc/qualcomm/sc7180/clock.c b/src/soc/qualcomm/sc7180/clock.c index aa289c4..4497b9c 100644 --- a/src/soc/qualcomm/sc7180/clock.c +++ b/src/soc/qualcomm/sc7180/clock.c @@ -164,12 +164,12 @@ pll_cfg.l_val = l_val; ret = clock_configure_enable_gpll(&pll_cfg, false, 0); - if (ret < 0) + if (ret != CB_SUCCESS) return CB_ERR; pll_cfg.reg_mode = &apss->pll.mode; ret = agera_pll_enable(&pll_cfg); - if (ret < 0) + if (ret != CB_SUCCESS) return CB_ERR; gfmux_val = read32(&apss->cfg_gfmux) & ~GFMUX_SRC_SEL_BMSK; @@ -224,7 +224,7 @@ if (clk_type >= MDSS_CLK_COUNT) return CB_ERR; - /* Enable clock*/ + /* Enable clock */ return clock_enable(mdss_cbcr[clk_type]); } -- To view, visit https://review.coreboot.org/c/coreboot/+/57447 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifabe0508a37a841779965f4e38172f680e18d38a Gerrit-Change-Number: 57447 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Taniya Das <tdas(a)codeaurora.org> Gerrit-Attention: Taniya Das <tdas(a)codeaurora.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: google/herobrine: configure gpio to detect board ID.
by Ravi kumar (Code Review) 07 Sep '21

07 Sep '21

Attention is currently required from: Ravi kumar, Sudheer Amrabadi, mturney mturney. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56642 to look at the new patch set (#7). Change subject: google/herobrine: configure gpio to detect board ID. ...................................................................... google/herobrine: configure gpio to detect board ID. read gpio value to get board ID. Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Change-Id: I6de2a7e7b11ecce8325e0fd44dc7221d73729390 --- M src/mainboard/google/herobrine/board.h M src/mainboard/google/herobrine/boardid.c 2 files changed, 7 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/56642/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/56642 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6de2a7e7b11ecce8325e0fd44dc7221d73729390 Gerrit-Change-Number: 56642 Gerrit-PatchSet: 7 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit September 2021