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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57369 )
Change subject: util/sconfig: Extract handling of SMBIOS data
......................................................................
Patch Set 2: Code-Review+2
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56777
to look at the new patch set (#6).
Change subject: soc/amd/common/block/i2c: use common GPIO API in drive_scl
......................................................................
soc/amd/common/block/i2c: use common GPIO API in drive_scl
No need to do raw GPIO MMIO accesses when basically the same
functionality can be achieved by using existing APIs. Using the existing
GPIO API instead of raw GPIO MMIO register accesses allows containing
all direct GPIO MMIO accesses inside the common AMD GPIO code which will
be done in subsequent patches. Since the value parameter of gpio_set is
int, change the type of the val parameter of drive_scl to int as well
even though I'm not sure why a signed integer was used for this in the
common GPIO API. Since program_gpios already configures the SCL GPIOs as
outputs, gpio_set can be used in drive_scl which only sets the output
value, but doesn't configure the direction.
TEST=The waveform on the SCL pin of I2C3 on a barla/careena Chromebook
looks similar to the same as before during the reset_i2c_peripherals
call, but due to the additional overhead of the read-modify-write to the
GPIO register instead of just a write, the pulse width gets about 50%
longer. Since the udelay call in drive_scl still has an open TODO to
make this configurable and the pulses being longer is in the safe side,
this side-effect can be addressed in a follow-up patch.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Ic323cebc1c83ecd6f0e1fbab419c69489d77face
---
M src/soc/amd/common/block/i2c/i2c.c
1 file changed, 7 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/56777/6
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55964 )
Change subject: src/mainboard/herobrine: Load GSI FW in ramstage
......................................................................
Patch Set 18:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/55964/comment/1165edb0_0eb2703e
PS18, Line 7: src/mainboard/herobrine
Please use the common prefixes.
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55376 )
Change subject: mainboard/google/herobrine: Increase the ROM size
......................................................................
Patch Set 21:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/55376/comment/40b3b859_96304c83
PS21, Line 7: mainboard/google/herobrine
mb/google/herobrine:
https://review.coreboot.org/c/coreboot/+/55376/comment/1d99487b_73607691
PS21, Line 7: Increase the ROM size
… to 64 MB
https://review.coreboot.org/c/coreboot/+/55376/comment/a2cde93d_6fd39641
PS21, Line 9: SPI NOR size should match with coreboot ROM size.
: On QCOM Piglin board SPI NOR size is 64MB and the
: default coreboot ROM size is 8MB. So, update coreboot
: ROM size to match with SPI NOR size.
Please reflow for 75 characters per line.
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