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Change subject: mb/google/trogdor: Add new variant Wormdingler
......................................................................
mb/google/trogdor: Add new variant Wormdingler
New boards introduced to trogdor family.
BUG=b:193870279
BRANCH=none
TEST=make
Change-Id: If3d9662e8725e30e1308d77b05545efbee29f846
Signed-off-by: Zanxi Chen <chenzanxi(a)huaqin.corp-partner.google.com>
---
M Documentation/security/vboot/list_vboot.md
M src/mainboard/google/trogdor/Kconfig
M src/mainboard/google/trogdor/Kconfig.name
3 files changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/56384/4
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Change subject: tests/Makefile.inc: Add function wrapping mechanism
......................................................................
tests/Makefile.inc: Add function wrapping mechanism
This patch extends mocks functionality to allowing wrapping of mocked
functions. Original function name will be prefixed with `__real_`.
Example:
- Mocked function: cbfs_lookup()
- New function name: __real_cbfs_lookup()
- Mock name: cbfs_lookup()
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Change-Id: I7cd0d66a17029955cbf75c8b155a7ebb7f5513aa
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M tests/Makefile.inc
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Paul F Yang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54673 )
Change subject: mb/google/dedede/var/galtic: Add charger throttling function
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
The code looks good, but I suggest to give precise current number for better understanding, like this;
register "controls.charger_perf" = "{
[0] = { 32, 2048 },
[1] = { 28, 1792 },
[2] = { 24, 1536 },
[3] = { 20, 1280 }
}"
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56461 )
Change subject: [TESTONLY]prodive/hermes: Try to run UART2 in ACPI mode
......................................................................
Patch Set 2:
(2 comments)
File src/soc/intel/common/block/uart/uart.c:
https://review.coreboot.org/c/coreboot/+/56461/comment/60ca8286_4afb2321
PS2, Line 120: 0xfe020000
> 0xFE032000
0xfe02000 + 0x2000 * PchSerialIoIndexUART0 = 0xfe032000. Btw do you know if this FSP specific behavior?
https://review.coreboot.org/c/coreboot/+/56461/comment/a2e3a30f_738f2e8a
PS2, Line 139: res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
> | IORESOURCE_RESERVE is missing
So why should that be needed in e820? Is that needed (or better) for non ACPI aware OS?
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Change subject: mb/*/jslrvp/dedede: Remove hardcoding of BSP APIC ID
......................................................................
mb/*/jslrvp/dedede: Remove hardcoding of BSP APIC ID
coreboot always assumes that BSP APIC ID will be 0 and core enumeration
logic will look for lapic id from the mainboard.
As per Intel 64 and IA-32 Architectures Software Developer’s Manual
Volume 3: 8.4.1 BSP and AP Processors, this assumption might
not hold true and we may have any other core as BSP. To handle this,
we need to remove hardcoding of APIC ID 0 from mainboard.
BUG=None
BRANCH=None
TEST=Check if there is no functional impact on the board.
Change-Id: I726d70b4ffc35a28a654abbd20c866f1410e1aee
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela(a)intel.com>
---
M src/mainboard/google/dedede/variants/baseboard/devicetree.cb
M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
2 files changed, 2 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/56759/3
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Change subject: [TESTONLY]prodive/hermes: Try to run UART2 in ACPI mode
......................................................................
Patch Set 2:
(2 comments)
File src/soc/intel/common/block/uart/uart.c:
https://review.coreboot.org/c/coreboot/+/56461/comment/76eebaaf_d66f95e1
PS2, Line 120: 0xfe020000
0xFE032000
https://review.coreboot.org/c/coreboot/+/56461/comment/ba4351b5_7c64c6e7
PS2, Line 139: res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
| IORESOURCE_RESERVE is missing
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Change subject: mb/google/octopus/var/phaser: Change IRQ trigger method to level
......................................................................
Patch Set 4: Code-Review+1
(1 comment)
Patchset:
PS4:
LGTM, differ to Marco to approve
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Change subject: mb/google/dedede/var/cret: Enable/disable Touchscreen based on FW_CONFIG
......................................................................
Abandoned
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Change subject: soc/intel/common/cpu: Handle non-zero BSP APIC ID in init_cpus
......................................................................
Patch Set 8:
(1 comment)
File src/soc/intel/common/block/cpu/mp_init.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-125742):
https://review.coreboot.org/c/coreboot/+/56758/comment/c461e915_53bc8ffa
PS8, Line 124: * creation of the new node will be skipped. This node will have the APIC ID defind in devicetree.
line over 96 characters
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I'd like you to reexamine a change. Please visit
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Change subject: [TESTONLY]prodive/hermes: Try to run UART2 in ACPI mode
......................................................................
[TESTONLY]prodive/hermes: Try to run UART2 in ACPI mode
When run in ACPI mode the BARs are at a fixed location in upper memory
according to the document 570374.
Change-Id: I1946c2db1385934a648702b6362eb1961de59e5a
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb
M src/soc/intel/common/block/uart/uart.c
2 files changed, 30 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/56461/2
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