Tao Xia has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56828 )
Change subject: mb/google/dedede/var/storo: Fixed iasl can not run on Dut
......................................................................
mb/google/dedede/var/storo: Fixed iasl can not run on Dut
The TSR1._PSV has been redefined.
It will report errors when disassembling the ACPI tables with the iasl.
It is OK when Removing the TSR1._PSV and adding the TSR0._PSV
BUG=b:194509417
BRANCH=dedede
TEST=The iasl can run on Dut successfully
Signed-off-by: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com>
Change-Id: I524255c79d3c71573d122944da5058389f79d95d
---
M src/mainboard/google/dedede/variants/storo/overridetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/56828/1
diff --git a/src/mainboard/google/dedede/variants/storo/overridetree.cb b/src/mainboard/google/dedede/variants/storo/overridetree.cb
index aedb285..90ad9ad 100644
--- a/src/mainboard/google/dedede/variants/storo/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/storo/overridetree.cb
@@ -86,7 +86,7 @@
chip drivers/intel/dptf
## Passive Policy
register "policies.passive" = "{
- [0] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 67, 3000),
+ [0] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 67, 3000),
[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 67, 3000),
[2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 67, 3000),}"
## Critical Policy
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Change subject: soc/intel/common: Calculate and configure SF Mask 2
......................................................................
Patch Set 7:
(1 comment)
File src/soc/intel/common/block/cpu/car/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/56717/comment/76c0dd06_6777e68c
PS5, Line 543: wrmsr
> CPU: ID 906a0, Alderlake Platform, ucode: 00000019 […]
@Tim, I have tried latest ucode as well, no issue seen on few units we have tested this patchtress.
coreboot-4.14-1299-g119097c-dirty Wed Aug 4 18:19:21 UTC 2021 bootblock starting (log level: 8)...
0xc91 hi =0 low = ffe
0x1891 hi =0 low = ffe
0xc92 hi =0 low = 1
0x1892 hi =0 low = 1
0xc85 hi =0 low = 1
0xc87 hi =0 low = c
CPU: Genuine Intel(R) 0000
CPU: ID 906a0, Alderlake Platform, ucode: 0000001c
CPU: AES supported, TXT supported, VT supported
Cache: Level 3: Associativity = 12 Partitions = 1 Line Size = 64 Sets = 16384
Cache: Size=12 MiB
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Hello build bot (Jenkins), Julius Werner, Jan Dabros,
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Change subject: tests/Makefile.inc: Add function wrapping mechanism
......................................................................
tests/Makefile.inc: Add function wrapping mechanism
This patch extends mocks functionality to allowing wrapping of mocked
functions. Original function name will be prefixed with `__real_`.
Example:
- Mocked function: cbfs_lookup()
- New function name: __real_cbfs_lookup()
- Mock name: cbfs_lookup()
Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com>
Change-Id: I7cd0d66a17029955cbf75c8b155a7ebb7f5513aa
---
M tests/Makefile.inc
1 file changed, 18 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/56719/6
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Change subject: mb/google/auron/var/lulu: Uniformise dual-channel handling
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
> looks sane, but likely moot as I don't believe LULU ever shipped in 2GB config, always 2+2 or 4+4
Good to know. This change merely uniformizes the code across all variants to ease factoring out redundant code in follow-ups.
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Change subject: mb/prodrive/hermes: Update HDA codec subvendor ID
......................................................................
Patch Set 3: Code-Review+2
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Change subject: mb/google/dedede/var/sasukette: Add fw_config probe for non-ext VR
......................................................................
Patch Set 3: Code-Review-1
(1 comment)
File src/mainboard/google/dedede/variants/sasukette/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/56804/comment/02a6be21_643d95eb
PS3, Line 2: ANPEC
this hasn't been applied and approved for now, please get it formally approved and implemented before carrying out the real changes. Thanks!
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Change subject: soc/mediatek/mt8192: initialize DFD
......................................................................
Patch Set 3:
(2 comments)
File src/soc/mediatek/mt8192/include/soc/dfd.h:
https://review.coreboot.org/c/coreboot/+/56797/comment/eea86d19_088700e9
PS2, Line 10: are also need
> need
Done
https://review.coreboot.org/c/coreboot/+/56797/comment/fe0ac174_70de79eb
PS2, Line 11: definiation
> as defined
Done
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I'd like you to reexamine a change. Please visit
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Change subject: soc/mediatek/mt8192: initialize DFD
......................................................................
soc/mediatek/mt8192: initialize DFD
DFD (Design for Debug) is a debugging tool, which scans
flip-flops and dumps to internal RAM on the WDT reset.
After system reboots, those values could be showed for
debugging.
Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com>
Change-Id: I39a4391c1d1e832d77b709f8f899bb1c6dcacd69
---
M src/soc/mediatek/mt8192/Kconfig
M src/soc/mediatek/mt8192/Makefile.inc
A src/soc/mediatek/mt8192/dfd.c
A src/soc/mediatek/mt8192/include/soc/dfd.h
M src/soc/mediatek/mt8192/soc.c
5 files changed, 46 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/56797/3
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Change subject: soc/mediatek/mt8192: initialize DFD
......................................................................
Patch Set 2:
(2 comments)
File src/soc/mediatek/mt8192/include/soc/dfd.h:
https://review.coreboot.org/c/coreboot/+/56797/comment/9d002368_575d4b18
PS2, Line 10: are also need
need
https://review.coreboot.org/c/coreboot/+/56797/comment/55376cdf_a08f9ddd
PS2, Line 11: definiation
as defined
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