coreboot-gerrit August 2021

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Change in coreboot[master]: mb/google/guybrush: Update GPIOs for fingerprint
by Martin Roth (Code Review) 12 Aug '21

12 Aug '21

Attention is currently required from: Raul Rangel, Karthik Ramasubramanian, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56499 ) Change subject: mb/google/guybrush: Update GPIOs for fingerprint ...................................................................... Patch Set 6: (6 comments) File src/mainboard/google/guybrush/mainboard.c: https://review.coreboot.org/c/coreboot/+/56499/comment/b153a214_307448e1 PS2, Line 181: > Nit: Extra indentation. Done File src/mainboard/google/guybrush/mainboard.c: https://review.coreboot.org/c/coreboot/+/56499/comment/b8e7169a_f80b53dd PS6, Line 181: variant_finalize_gpios(); > Nit: extra tab Done File src/mainboard/google/guybrush/variants/baseboard/gpio.c: https://review.coreboot.org/c/coreboot/+/56499/comment/61014d24_a3d0d774 PS6, Line 69: /* EN_PWR_FP */ > Nit: Retain that comment/Pin Info Done https://review.coreboot.org/c/coreboot/+/56499/comment/7dcc4be1_5611ebdf PS6, Line 358: /* : * If the system is not resuming from S3, power off the FPMCU : */ > Nit: Single line comment. Done https://review.coreboot.org/c/coreboot/+/56499/comment/3641b33b_b67478b4 PS6, Line 373: /* FPMCU_RST_L */ : PAD_NC(GPIO_11), : /* EN_PWR_FP */ : > Nit: Extra tabs Done https://review.coreboot.org/c/coreboot/+/56499/comment/bf0a0228_4ee09ceb PS6, Line 386: gpio_set(GPIO_32, 1); /* EN_PWR_FP */ : mdelay(3); > Since the EN_PWR_FP is already set HIGH at the start of ramstage, do we still need to reset it and d […] Good call, no we can get rid of this now. Done. -- To view, visit https://review.coreboot.org/c/coreboot/+/56499 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaae5feec60abb2480777d1f99174254c5132bb43 Gerrit-Change-Number: 56499 Gerrit-PatchSet: 6 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 11 Aug 2021 20:48:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Update GPIOs for fingerprint
by Martin Roth (Code Review) 12 Aug '21

12 Aug '21

Attention is currently required from: Raul Rangel, Martin Roth, Felix Held. Hello build bot (Jenkins), Paul Menzel, Karthik Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56499 to look at the new patch set (#7). Change subject: mb/google/guybrush: Update GPIOs for fingerprint ...................................................................... mb/google/guybrush: Update GPIOs for fingerprint Add mainboard finalize and shutdown call to match zork. Deassert EN_PWR_FP in bootblock, power up correctly in finalize. | Phase | SOC_FP_RST_L | EN_PWR_FP | S3 resume | |-----------|--------------|-----------|----------------------| | Bootblock | **Low** | **Low** | Maintain High / High | | Romstage | Low | Low | Maintain High / High | | Ramstage | Low | **High** | Maintain High / High | | Finalize | **High** | High | | | Shutdown | **Low** | **Low** | | BUG=b:191694480 TEST=Build, verify GPIO configuration. Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: Iaae5feec60abb2480777d1f99174254c5132bb43 --- M src/mainboard/google/guybrush/mainboard.c M src/mainboard/google/guybrush/variants/baseboard/gpio.c M src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h 3 files changed, 46 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/56499/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/56499 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaae5feec60abb2480777d1f99174254c5132bb43 Gerrit-Change-Number: 56499 Gerrit-PatchSet: 7 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/guybrush: Update GPIOs for fingerprint
by Karthik Ramasubramanian (Code Review) 12 Aug '21

12 Aug '21

Attention is currently required from: Raul Rangel, Martin Roth, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56499 ) Change subject: mb/google/guybrush: Update GPIOs for fingerprint ...................................................................... Patch Set 6: (6 comments) File src/mainboard/google/guybrush/mainboard.c: https://review.coreboot.org/c/coreboot/+/56499/comment/50ea45eb_69034fda PS2, Line 181: Nit: Extra indentation. File src/mainboard/google/guybrush/mainboard.c: https://review.coreboot.org/c/coreboot/+/56499/comment/cc6925e3_acb00ee6 PS6, Line 181: variant_finalize_gpios(); Nit: extra tab File src/mainboard/google/guybrush/variants/baseboard/gpio.c: https://review.coreboot.org/c/coreboot/+/56499/comment/215b0e16_6f1fcb41 PS6, Line 69: /* EN_PWR_FP */ Nit: Retain that comment/Pin Info https://review.coreboot.org/c/coreboot/+/56499/comment/fb50845d_a8d91c20 PS6, Line 358: /* : * If the system is not resuming from S3, power off the FPMCU : */ Nit: Single line comment. https://review.coreboot.org/c/coreboot/+/56499/comment/96e0b548_6450fb06 PS6, Line 373: /* FPMCU_RST_L */ : PAD_NC(GPIO_11), : /* EN_PWR_FP */ : Nit: Extra tabs https://review.coreboot.org/c/coreboot/+/56499/comment/b404a688_fec3c65a PS6, Line 386: gpio_set(GPIO_32, 1); /* EN_PWR_FP */ : mdelay(3); Since the EN_PWR_FP is already set HIGH at the start of ramstage, do we still need to reset it and do we still need the delay? -- To view, visit https://review.coreboot.org/c/coreboot/+/56499 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaae5feec60abb2480777d1f99174254c5132bb43 Gerrit-Change-Number: 56499 Gerrit-PatchSet: 6 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 11 Aug 2021 20:30:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common: Skip psp_verstage on S0i3 resume
by Furquan Shaikh (Code Review) 12 Aug '21

12 Aug '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson, Felix Held. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56919 ) Change subject: soc/amd/common: Skip psp_verstage on S0i3 resume ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/common/psp_verstage/psp_verstage.c: https://review.coreboot.org/c/coreboot/+/56919/comment/44b2b7a4_41218cb3 PS1, Line 205: Currently, we want to skip running verstage on all S0i3 resumes. This relies : on an assumption that the PSP will be checksumming all of its components. If verstage must not run on S0i3 resume, then I would expect PSP BL to not load this component at all. Why verify and load this component when it is not going to do anything? -- To view, visit https://review.coreboot.org/c/coreboot/+/56919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7b2560ff3d7621922ec4bc0e8793961f5d7550f Gerrit-Change-Number: 56919 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 11 Aug 2021 20:17:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common: Skip psp_verstage on S0i3 resume
by Martin Roth (Code Review) 12 Aug '21

12 Aug '21

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56919 ) Change subject: soc/amd/common: Skip psp_verstage on S0i3 resume ...................................................................... soc/amd/common: Skip psp_verstage on S0i3 resume BUG=b:177064859 TEST:Verify that S0i3 doesn't run on S0i3 resume Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: Ia7b2560ff3d7621922ec4bc0e8793961f5d7550f --- M src/soc/amd/common/psp_verstage/psp_verstage.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/56919/1 diff --git a/src/soc/amd/common/psp_verstage/psp_verstage.c b/src/soc/amd/common/psp_verstage/psp_verstage.c index 5c59c4f..98df0a6 100644 --- a/src/soc/amd/common/psp_verstage/psp_verstage.c +++ b/src/soc/amd/common/psp_verstage/psp_verstage.c @@ -200,6 +200,13 @@ { uint32_t retval; struct vb2_context *ctx = NULL; + uint32_t bootmode = 0; + + /* Currently, we want to skip running verstage on all S0i3 resumes. This relies + on an assumption that the PSP will be checksumming all of its components. */ + svc_get_boot_mode(&bootmode); + if (bootmode == PSP_BOOT_MODE_S0i3_RESUME) + svc_exit(0); /* * Do not use printk() before console_init() -- To view, visit https://review.coreboot.org/c/coreboot/+/56919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7b2560ff3d7621922ec4bc0e8793961f5d7550f Gerrit-Change-Number: 56919 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/variant/taeko: Update devicetree settings
by Tim Wawrzynczak (Code Review) 12 Aug '21

12 Aug '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56802 ) Change subject: mb/google/brya/variant/taeko: Update devicetree settings ...................................................................... mb/google/brya/variant/taeko: Update devicetree settings Based on schematic and gpio table of taeko, generate overridetree.cb settings for taeko. BUG=b:195494281 TEST=FW_NAME=taeko emerge-brya coreboot chromeos-bootimage Signed-off-by: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Change-Id: I96aaf48284a226edc39115f870bf0f3dd83ab8b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56802 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/taeko/overridetree.cb 1 file changed, 277 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb index 4f2c04a..a8a5e83 100644 --- a/src/mainboard/google/brya/variants/taeko/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb @@ -1,6 +1,281 @@ chip soc/intel/alderlake + register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable Port 1 + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)" # DB USB2_C1 + register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable M.2 WWAN + register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Disable M.2 WWAN - device domain 0 on - end + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| GSPI1 | Fingerprint MCU | + #| I2C0 | Audio | + #| I2C1 | Touchscreen | + #| I2C2 | HPS | + #| I2C3 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config.chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT" + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + # I2C Port Config + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + device domain 0 on + device ref tbt_pcie_rp0 off end + device ref tbt_pcie_rp1 off end + device ref tbt_pcie_rp2 off end + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on + end + end + end + device ref i2c1 on + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + # Parameter T5 >= 180ms + register "generic.reset_delay_ms" = "180" + # Parameter T2 >= 1ms + register "generic.reset_off_delay_ms" = "3" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + # Parameter T1 >= 20ms + register "generic.enable_delay_ms" = "20" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E3)" + # Parameter T4 >= 1ms + register "generic.stop_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 5d on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "probed" = "1" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "reset_delay_ms" = "20" + register "enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "enable_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 10 on end + end + end + device ref i2c5 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "wake" = "GPE0_DW2_15" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "generic.wake" = "GPE0_DW2_15" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end + device ref hda on + chip drivers/generic/max98357a + register "hid" = ""MX98357A"" + register "sdmode_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" + register "sdmode_delay" = "5" + device generic 0 on end + end + chip drivers/intel/soundwire + device generic 0 on + chip drivers/soundwire/alc5682 + # SoundWire Link 0 ID 1 + register "desc" = ""Headset Codec"" + device generic 0.1 on end + end + chip drivers/soundwire/max98373 + # SoundWire Link 2 ID 3 + register "desc" = ""Left Speaker Amp"" + device generic 2.3 on end + end + chip drivers/soundwire/max98373 + # SoundWire Link 2 ID 7 + register "desc" = ""Right Speaker Amp"" + device generic 2.7 on end + end + end + end + end + device ref pcie_rp5 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H20)" + register "srcclk_pin" = "2" + device generic 0 on end + end + register "pch_pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref pcie_rp6 off end + device ref pcie_rp8 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)" + register "srcclk_pin" = "3" + device generic 0 on end + end + end + device ref pcie_rp9 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" + register "srcclk_pin" = "1" + device generic 0 on end + end + end + device ref gspi1 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)" + register "wake" = "GPE0_DW2_15" + device spi 0 on end + end # FPMCU + end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "1" + register "usb3_port_number" = "1" + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "3" + register "usb3_port_number" = "3" + device generic 2 alias conn1 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref tcss_usb3_port3 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port6 on + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port (MLB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(4, 1)" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(4, 1)" + device ref usb3_port1 on end + end + end + end + end + end end -- To view, visit https://review.coreboot.org/c/coreboot/+/56802 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96aaf48284a226edc39115f870bf0f3dd83ab8b4 Gerrit-Change-Number: 56802 Gerrit-PatchSet: 17 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/variant/taeko: Update devicetree settings
by Tim Wawrzynczak (Code Review) 12 Aug '21

12 Aug '21

Attention is currently required from: Joey Peng. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56802 ) Change subject: mb/google/brya/variant/taeko: Update devicetree settings ...................................................................... Patch Set 16: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56802 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96aaf48284a226edc39115f870bf0f3dd83ab8b4 Gerrit-Change-Number: 56802 Gerrit-PatchSet: 16 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-Attention: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Comment-Date: Wed, 11 Aug 2021 19:28:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Implement report_cache_info() function
by Subrata Banik (Code Review) 12 Aug '21

12 Aug '21

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55654 ) Change subject: soc/intel/alderlake: Implement report_cache_info() function ...................................................................... soc/intel/alderlake: Implement report_cache_info() function Make use of deterministic cache helper functions from Alder Lake SoC code to print useful information during boot as below: Cache: Level 3: Associativity = 12 Partitions = 1 Line Size=64 Sets=16384 Cache size = 12 MiB Change-Id: I30a56266015d69abccb885b3f230689488ee0360 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55654 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/alderlake/bootblock/report_platform.c 1 file changed, 18 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c index 4e071e7..b7d4cfc 100644 --- a/src/soc/intel/alderlake/bootblock/report_platform.c +++ b/src/soc/intel/alderlake/bootblock/report_platform.c @@ -8,6 +8,7 @@ #include <arch/cpu.h> #include <device/pci_ops.h> +#include <commonlib/helpers.h> #include <console/console.h> #include <cpu/intel/cpu_ids.h> #include <cpu/intel/microcode.h> @@ -120,6 +121,21 @@ return pci_read_config16(dev, PCI_DEVICE_ID); } +static void report_cache_info(void) +{ + int cache_level = CACHE_L3; + struct cpu_cache_info info; + + if (!fill_cpu_cache_info(cache_level, &info)) + return; + + printk(BIOS_INFO, "Cache: Level %d: ", cache_level); + printk(BIOS_INFO, "Associativity = %zd Partitions = %zd Line Size = %zd Sets = %zd\n", + info.num_ways, info.physical_partitions, info.line_size, info.num_sets); + + printk(BIOS_INFO, "Cache size = %ld MiB\n", get_cache_size(&info)/MiB); +} + static void report_cpu_info(void) { u32 i, cpu_id, cpu_feature_flag; @@ -150,6 +166,8 @@ printk(BIOS_DEBUG, "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n", mode[aes], mode[txt], mode[vt]); + + report_cache_info(); } static void report_mch_info(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/55654 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30a56266015d69abccb885b3f230689488ee0360 Gerrit-Change-Number: 55654 Gerrit-PatchSet: 10 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/variants/brya0: add PL4 values for different SKUs
by Tim Wawrzynczak (Code Review) 12 Aug '21

12 Aug '21

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Change in coreboot[master]: mb/google/brya: set PL4 value dynamically for thermal
by Tim Wawrzynczak (Code Review) 12 Aug '21

12 Aug '21

Attention is currently required from: Furquan Shaikh, Sumeet R Pawnikar, Karthik Ramasubramanian. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56915 ) Change subject: mb/google/brya: set PL4 value dynamically for thermal ...................................................................... Patch Set 1: (2 comments) File src/mainboard/google/brya/variants/baseboard/brya/ramstage.c: https://review.coreboot.org/c/coreboot/+/56915/comment/233c0311_5091f71f PS1, Line 29: struct soc_power_limits_config *soc_config; : config_t *conf = config_of_soc(); : soc_config = conf->power_limits_config; nit: this can go down below line 37, and be simplified to: ``` struct soc_power_limits_config *soc_config = config_of_soc()->power_limits_config; soc_config->tdp_pl4... ``` https://review.coreboot.org/c/coreboot/+/56915/comment/ec813f10_a886666e PS1, Line 43: DPTF DPTF does not control PL4, so I would drop that acronym here. -- To view, visit https://review.coreboot.org/c/coreboot/+/56915 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20b98ccd8493ed238de647cda8ceb25f62029133 Gerrit-Change-Number: 56915 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 11 Aug 2021 19:08:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit August 2021