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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: [Test] adlrvp: Disable HD audio for pnp measurements
......................................................................
[Test] adlrvp: Disable HD audio for pnp measurements
Change-Id: I40ccf48c51c52d253b98a8ccbea294b65a2e306b
---
M src/mainboard/intel/adlrvp/Kconfig
M src/mainboard/intel/adlrvp/devicetree_m.cb
M src/mainboard/intel/adlrvp/mainboard.c
3 files changed, 4 insertions(+), 82 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/56922/2
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Change subject: mb/google/brya: Configure A17 GPIO to high
......................................................................
Patch Set 3: Code-Review+2
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Change subject: mb/google/octopus/var/phaser: Change IRQ trigger method to level
......................................................................
Patch Set 4: Code-Review+1
(1 comment)
Patchset:
PS4:
I am good for this CL since vendor provided that spec defined it should be level triggered. But please address other reviewer's comments then I would be good to +2. Thanks.
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Change subject: test for codec ALC5682I-VD & VS compatibility
......................................................................
Patch Set 2:
(3 comments)
This change is ready for review.
Commit Message:
https://review.coreboot.org/c/coreboot/+/56914/comment/367476b9_df660949
PS1, Line 7: ALC5782I
> ALC5682I
Done
https://review.coreboot.org/c/coreboot/+/56914/comment/86daa554_8aca37b8
PS1, Line 11: ALC5782I
> ALC5682I
Done
File src/drivers/i2c/rt5682/rt5682.c:
https://review.coreboot.org/c/coreboot/+/56914/comment/23209ca6_6290af9f
PS1, Line 60:
> delete
Done
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Frank Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56924 )
Change subject: mb/google/dedede/var/driblee: Generate RAM ID and SPD file
......................................................................
mb/google/dedede/var/driblee: Generate RAM ID and SPD file
Add the support RAM parts for Driblee.
Here is the ram part number list:
1. Hynix H9HCNNNBKMMLXR-NEE
2. Micron MT53E512M32D2NP-046 WT:F
3. Samsung K4U6E3S4AA-MGCR
4. Micron MT53E512M32D1NP-046 WT:B
BUG=b:195619346
BRANCH=keeby
TEST=emerge-keeby coreboot
Signed-off-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com>
Change-Id: I683acb91ec13cbd772e732d7f81152ceb3cefc1c
---
M src/mainboard/google/dedede/variants/driblee/memory/Makefile.inc
M src/mainboard/google/dedede/variants/driblee/memory/dram_id.generated.txt
M src/mainboard/google/dedede/variants/driblee/memory/mem_parts_used.txt
3 files changed, 10 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/56924/1
diff --git a/src/mainboard/google/dedede/variants/driblee/memory/Makefile.inc b/src/mainboard/google/dedede/variants/driblee/memory/Makefile.inc
index b0ca222..42c6cf4 100644
--- a/src/mainboard/google/dedede/variants/driblee/memory/Makefile.inc
+++ b/src/mainboard/google/dedede/variants/driblee/memory/Makefile.inc
@@ -1,5 +1,5 @@
## SPDX-License-Identifier: GPL-2.0-or-later
## This is an auto-generated file. Do not edit!!
-## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate.
-SPD_SOURCES = placeholder.spd.hex
+SPD_SOURCES =
+SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = H9HCNNNBKMMLXR-NEE, MT53E512M32D2NP-046 WT:F, K4U6E3S4AA-MGCR, MT53E512M32D1NP-046 WT:B
diff --git a/src/mainboard/google/dedede/variants/driblee/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/driblee/memory/dram_id.generated.txt
index fa24790..0dbc38e 100644
--- a/src/mainboard/google/dedede/variants/driblee/memory/dram_id.generated.txt
+++ b/src/mainboard/google/dedede/variants/driblee/memory/dram_id.generated.txt
@@ -1 +1,5 @@
DRAM Part Name ID to assign
+H9HCNNNBKMMLXR-NEE 0 (0000)
+MT53E512M32D2NP-046 WT:F 0 (0000)
+K4U6E3S4AA-MGCR 0 (0000)
+MT53E512M32D1NP-046 WT:B 0 (0000)
diff --git a/src/mainboard/google/dedede/variants/driblee/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/driblee/memory/mem_parts_used.txt
index e4258b5..c1e9e0c 100644
--- a/src/mainboard/google/dedede/variants/driblee/memory/mem_parts_used.txt
+++ b/src/mainboard/google/dedede/variants/driblee/memory/mem_parts_used.txt
@@ -1,11 +1,4 @@
-# This is a CSV file containing a list of memory parts used by this variant.
-# One part per line with an optional fixed ID in column 2.
-# Only include a fixed ID if it is required for legacy reasons!
-# Generated IDs are dependent on the order of parts in this file,
-# so new parts must always be added at the end of the file!
-#
-# Generate an updated Makefile.inc and dram_id.generated.txt by running the
-# gen_part_id tool from util/spd_tools/{ddr4,lp4x}.
-# See util/spd_tools/{ddr4,lp4x}/README.md for more details and instructions.
-
-# Part Name
+H9HCNNNBKMMLXR-NEE
+MT53E512M32D2NP-046 WT:F
+K4U6E3S4AA-MGCR
+MT53E512M32D1NP-046 WT:B
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Change subject: cezanne/fw.cfg: Remove two FWs from amdfw.rom
......................................................................
Patch Set 12:
(1 comment)
Patchset:
PS8:
> Add a comment is fw. […]
Add a comment in fw.cfg
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Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56587 )
Change subject: qualcomm/sc7180: Cleanups for drivers with common clock
......................................................................
Patch Set 5:
(6 comments)
File src/soc/qualcomm/sc7180/clock.c:
https://review.coreboot.org/c/coreboot/+/56587/comment/5334a964_770664cd
PS5, Line 131: int
When using the CB_xxx error values, please use the return type `enum cb_err` instead of a standard integer type (applies to multiple functions in here).
https://review.coreboot.org/c/coreboot/+/56587/comment/7a072c5f_f52154b9
PS5, Line 172: while
This should be an `if` now
https://review.coreboot.org/c/coreboot/+/56587/comment/b07c81d4_c6464011
PS5, Line 183: while
same
https://review.coreboot.org/c/coreboot/+/56587/comment/a2ded891_7d77478c
PS5, Line 311: if (ret < 0)
If you want to use the cb_err type, use it consistently (i.e. this should check `if (ret != CB_SUCCESS)` or something like that. Never treat cb_err as an integer or mix it with integers in the same variable.
https://review.coreboot.org/c/coreboot/+/56587/comment/81b36a5b_9a2ff87a
PS5, Line 356: divider
nit: Would be easier to just say `divider * 2 - 1` here?
File src/soc/qualcomm/sc7180/watchdog.c:
https://review.coreboot.org/c/coreboot/+/56587/comment/6eef91de_c68b07e4
PS5, Line 8: #define WDOG_RESET_BIT_MASK 1
If you add this here you also should remove it from clock.h in this same patch.
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