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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56882 )
Change subject: mb/google/brya: Configure A17 GPIO to high
......................................................................
Patch Set 3:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56882/comment/c37c2236_5d1bdbab
PS3, Line 7: Configure A17 GPIO to high
Use 3.3 V for USB UFC
https://review.coreboot.org/c/coreboot/+/56882/comment/8d221883_328805db
PS3, Line 9: Recent change https://review.coreboot.org/c/coreboot/+/56655
As it’s merged already, please reference the commit hash and summary.
https://review.coreboot.org/c/coreboot/+/56882/comment/ee5d263c_475bf30a
PS3, Line 11: probing, however
probing. Hower
https://review.coreboot.org/c/coreboot/+/56882/comment/0493b258_9c37a4c7
PS3, Line 12: by A17, this caused USB UFC enumeration to fail
Please add dot/period at the end of sentences.
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Hello build bot (Jenkins), Furquan Shaikh, Maulik V Vaghela, Paul Menzel, Subrata Banik,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56881
to look at the new patch set (#7).
Change subject: mb/intel/adlrvp: Update DIMM type as memory down for DDR5 MR SKU
......................................................................
mb/intel/adlrvp: Update DIMM type as memory down for DDR5 MR SKU
DDR5 Maple Ridge SKU (Board ID 0x16) uses a Memory down DIMM
configuration.
TEST=Boot DDR5 MR SKU to OS.
Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com>
Change-Id: I0b7a96b5534d8b80776aa7578ce7c13181af7882
---
M src/mainboard/intel/adlrvp/romstage_fsp_params.c
M src/mainboard/intel/adlrvp/spd/Makefile.inc
A src/mainboard/intel/adlrvp/spd/adlrvp_ddr5_mr.spd.hex
3 files changed, 34 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/56881/7
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56750 )
Change subject: vc/google/chromeos: Add support for new SAR tables revisions
......................................................................
Patch Set 10:
(6 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56750/comment/a42383a6_f4ebe36f
PS10, Line 12:
Please summarize the differences to version 1 and the implementation (antgain, …). Why does the vendor code need to be changed at the same time?
https://review.coreboot.org/c/coreboot/+/56750/comment/954b383c_251596d7
PS10, Line 14: TEST=Check the generated SSDT tables on brya
How exactlys
File src/drivers/wifi/generic/Kconfig:
https://review.coreboot.org/c/coreboot/+/56750/comment/b4228734_047581f5
PS10, Line 29: Enable it when wifi driver uses wifi6e/DSM configuration feature.
Can both be used at the same time? Is there a way to autodetect the version?
File src/drivers/wifi/generic/acpi.c:
https://review.coreboot.org/c/coreboot/+/56750/comment/f37538f9_e43577f3
PS10, Line 57: printk(BIOS_DEBUG, "failed from getting SAR limits!\n");
Reword to “failed getting SAR limits!” could be separate commit.
https://review.coreboot.org/c/coreboot/+/56750/comment/fb67473f_25c8a007
PS10, Line 135: package_size
size_t
https://review.coreboot.org/c/coreboot/+/56750/comment/a2d7002c_4a89892c
PS10, Line 221: int i, package_size;
size_t
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Change subject: mb/google/dedede: add gooey variant
......................................................................
Patch Set 8:
(4 comments)
This change is ready for review.
File src/mainboard/google/dedede/variants/gooey/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/56858/comment/3b652a5c_af09769e
PS3, Line 11: #| I2C5 | P-Sensor |
> Nit: Please fix the indentation.
Done
https://review.coreboot.org/c/coreboot/+/56858/comment/0b537216_5ae23950
PS3, Line 18: .scl_lcnt = 190,
: .scl_hcnt = 100,
: .sda_hold = 40,
> Coreboot recommendation is to configure rise_time_ns and fall_time_ns. […]
The proto phase of Gooey project for debug and test from 8/23, and Gooey motherboard just shipment from factory side. We will update I2C rise_time_ns and fall_time_ns after EE tuning in proto/EVT phase. Could you approve if we update the item in next CL?
https://review.coreboot.org/c/coreboot/+/56858/comment/517fb1db_ae940815
PS3, Line 68:
> register "SerialIoGSpiMode[PchSerialIoIndexGSPI0]" = "PchSerialIoDisabled" # Disable GSPI0 […]
Done
https://review.coreboot.org/c/coreboot/+/56858/comment/38d96348_fa0848e1
PS3, Line 334: end # PCH eSPI
> Disable GSPI 0
Done
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Change subject: drivers/wifi/generic: Enable DSM ACPI entries for Intel WIFI card
......................................................................
Patch Set 10:
(2 comments)
Patchset:
PS10:
Can the vendorcode change be split out?
File src/drivers/wifi/generic/acpi.c:
https://review.coreboot.org/c/coreboot/+/56751/comment/c1818118_37b20ef0
PS10, Line 41: /* Unique ID for the WIFI _DSM. */
Please remove the dot/period.
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Change subject: mb/google/octopus/var/phaser: Change IRQ trigger method to level
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56380/comment/1b315347_d2715ae9
PS4, Line 14:
> According to Marco's comment, change this comment to resolved
This is the information (that is was copied and never used) I’d like to have in the commit message.
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