Attention is currently required from: Felix Singer, Angel Pons, Michael Niewöhner, Patrick Rudolph.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56664 )
Change subject: soc/intel/cannonlake: Report correct latencies for C states
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56664/comment/9142b3d5_10fb1787
PS1, Line 7: correct
> As per which source of information?
What we program to the hardware, actually. cf. CB:56662, and skylake/ (it's the same silicon, basically)
The programmed values are given by the SKL/KBL/CFL/CML BWG.
https://review.coreboot.org/c/coreboot/+/56664/comment/d0dd03b1_40007b2f
PS1, Line 8:
> tested? if yes, how?
Well, we do run everything on our current hardware target Roda/RW14.
But I don't know if this counts as testing. Most of the values in this
table are never read (see below, only C1E C6_LONG_LAT, C7_LONG_LAT
and C10 are). And I don't know if Linux consumes the values. The whole
code here seems a bit overengineered. Which makes it hard to use any-
thing but the recommended values, blindly.
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56380 )
Change subject: mb/google/octopus/var/phaser: Change IRQ trigger method to level
......................................................................
mb/google/octopus/var/phaser: Change IRQ trigger method to level
The change from Synaptics S7817 to Elan 3915N and pin distribution
of touch IC is the same.
The original Elan section was copied from reference design and
was never used before.
According to vendor spec definition IRQ trigger method needs to
change to level.
BUG=b:190574692
TEST=Build coreboot and check that device works
Change-Id: I44ee779242779c78ceafdddd34dca2571e714dd3
Signed-off-by: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56380
Reviewed-by: Marco Chen <marcochen(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/google/octopus/variants/phaser/overridetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Marco Chen: Looks good to me, approved
diff --git a/src/mainboard/google/octopus/variants/phaser/overridetree.cb b/src/mainboard/google/octopus/variants/phaser/overridetree.cb
index 45c017a..ae52c3d 100644
--- a/src/mainboard/google/octopus/variants/phaser/overridetree.cb
+++ b/src/mainboard/google/octopus/variants/phaser/overridetree.cb
@@ -150,7 +150,7 @@
chip drivers/i2c/generic
register "hid" = ""ELAN0001""
register "desc" = ""ELAN Touchscreen""
- register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)"
+ register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)"
register "probed" = "1"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)"
register "reset_delay_ms" = "20"
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Hello build bot (Jenkins), Henry Sun, Paul Menzel, Weimin Wu, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/dedede/var/sasukette: Add fw_config probe for non-ext VR
......................................................................
mb/google/dedede/var/sasukette: Add fw_config probe for non-ext VR
Refer to commit df520855
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Add fw_config probe for don't stuffing ANPEC APW8738BQBI IC.
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M src/mainboard/google/dedede/variants/sasukette/ramstage.c
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Hello build bot (Jenkins), Henry Sun, Paul Menzel, Weimin Wu, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/dedede/var/sasukette: Add fw_config probe for non-ext VR
......................................................................
mb/google/dedede/var/sasukette: Add fw_config probe for non-ext VR
Refer to commit df520855
(soc/intel/jsl: Add disable_external_bypass_vr config)
Add fw_config probe for don't stuffing ANPEC APW8738BQBI IC.
BUG=b:190727416
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Signed-off-by: Zhi Li <lizhi7(a)huaqin.corp-partner.google.com>
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---
M src/mainboard/google/dedede/variants/baseboard/devicetree.cb
M src/mainboard/google/dedede/variants/sasukette/ramstage.c
2 files changed, 14 insertions(+), 0 deletions(-)
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56993 )
Change subject: soc/intel/alderlake: Move INTEL_CAR_NEM selection from SoC to mainboard
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56993/comment/f1bf2e4e_be7393a6
PS1, Line 11: feature on OEM/ODM reference designs.
> Were problems observed?
its kind of precaution steps so we don't want to run into the issue and be in catching situation.
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56662 )
Change subject: Revert "src/soc/intel/cannonlake: Update C-state latency control limits"
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56662/comment/88ef3fd1_82b4b5cb
PS1, Line 14:
> It should work therotically, if you have made all the changes to match that of soc/skylake. […]
Alas, I don't have the hardware to confirm the S0ix status.
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Nico Huber has uploaded a new patch set (#2) to the change originally created by Felix Singer. ( https://review.coreboot.org/c/coreboot/+/56662 )
Change subject: Revert "src/soc/intel/cannonlake: Update C-state latency control limits"
......................................................................
Revert "src/soc/intel/cannonlake: Update C-state latency control limits"
This reverts commit 66dbb0c5d67279722fcbcb547d9c6b61e606d50e.
The numbers were meant for Cannon Lake, but the code was also meant
to be used for all other platforms using the Cannon Point PCH. Now
Cannon Lake support is even dropped, so we can cleanly revert to the
recommended values for the other platforms.
Change-Id: Iea56c6a29ca4b34c9852393fed2e3be4de128ec6
Signed-off-by: Nico Huber <nico.huber(a)secunet.com>
---
M src/soc/intel/cannonlake/cpu.c
M src/soc/intel/cannonlake/include/soc/cpu.h
2 files changed, 17 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/56662/2
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