Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/57000 )
Change subject: mb/google/brya: set tcc_offset value to 10
......................................................................
mb/google/brya: set tcc_offset value to 10
Set tcc_offset value to 10 in devicetree for Thermal Control
Circuit (TCC) activation feature.
BUGb=b:195706434
BRANCH=None
TEST=Built for brya platform and verified the MSR value
Change-Id: I22573e8ca935d99a16b0876768df169db4e61c4d
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com>
---
M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/57000/1
diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
index 3281902..762aa84 100644
--- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
@@ -19,6 +19,8 @@
# DPTF enable
register "dptf_enable" = "1"
+ register "tcc_offset" = "10" # TCC of 90
+
# Enable heci communication
register "HeciEnabled" = "1"
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56904 )
Change subject: include/bcd: move bcd code to commonlib/bsd/include
......................................................................
Patch Set 3: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56904/comment/49e9b920_b4b5f222
PS3, Line 14: For reference bin2bcd() &
Nit: Why wrap the line here?
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Frank Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56997 )
Change subject: mb/google/dedede/var/driblee: Configure USB port settings
......................................................................
mb/google/dedede/var/driblee: Configure USB port settings
Update the USB port configuration based on driblee schematic.
USB2 [0]: USB Type C Port 0
USB2 [1]: None
USB2 [2]: USB Type A Port 1
USB2 [3]: None
USB2 [4]: None
USB2 [5]: Camera UFC
USB2 [6]: None
USB2 [7]: None
USB3 [0]: USB Type C Port 0 (M/B side)
USB3 [1]: None
USB3 [2]: USB Type A Port 0 (M/B side)
USB3 [3]: None
BUG=b:195622487, b:191732473
BRANCH=keeby
TEST=FW_NAME="driblee" emerge-keeby coreboot
Signed-off-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com>
Change-Id: Id9f4f8db98cb20db1c3936c65689a847a7802b9a
---
M src/mainboard/google/dedede/variants/driblee/overridetree.cb
1 file changed, 32 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/56997/1
diff --git a/src/mainboard/google/dedede/variants/driblee/overridetree.cb b/src/mainboard/google/dedede/variants/driblee/overridetree.cb
index cbad0d2..6fbd537 100644
--- a/src/mainboard/google/dedede/variants/driblee/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/driblee/overridetree.cb
@@ -1,5 +1,14 @@
chip soc/intel/jasperlake
+ # USB Port Configuration
+ register "usb2_ports[1]" = "USB2_PORT_EMPTY" # None
+ register "usb2_ports[3]" = "USB2_PORT_EMPTY" # None
+ register "usb2_ports[4]" = "USB2_PORT_EMPTY" # None
+ register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera (UFC)
+ register "usb2_ports[6]" = "USB2_PORT_EMPTY" # None
+ register "usb3_ports[1]" = "USB3_PORT_EMPTY" # None
+ register "usb3_ports[3]" = "USB3_PORT_EMPTY" # None
+
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
@@ -32,6 +41,29 @@
register "SerialIoGSpiCsMode[PchSerialIoIndexGSPI0]" = "0"
device domain 0 on
+ device pci 14.0 on
+ chip drivers/usb/acpi
+ device usb 0.0 on
+ chip drivers/usb/acpi
+ device usb 2.1 off end
+ end
+ chip drivers/usb/acpi
+ device usb 2.3 off end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""Camera (UFC)""
+ register "type" = "UPC_TYPE_INTERNAL"
+ device usb 2.5 on end
+ end
+ chip drivers/usb/acpi
+ device usb 3.1 off end
+ end
+ chip drivers/usb/acpi
+ device usb 3.3 off end
+ end
+ end
+ end
+ end # USB xHCI
device pci 15.0 on end
device pci 1e.2 off end # GSPI 0
device pci 1f.0 on
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Hello build bot (Jenkins), Henry Sun,
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Change subject: mb/google/dedede/var/sasukette: Add fw_config probe for non-ext VR
......................................................................
mb/google/dedede/var/sasukette: Add fw_config probe for non-ext VR
commit df520855 (soc/intel/jsl: Add disable_external_bypass_vr config)
Add fw_config probe for don't stuffing ANPEC APW8738BQBI IC.
BUG=b:190727416
BRANCH=dedede
TEST=test for enter S0ix and resume normally by powerd_dbus_suspend
Signed-off-by: Zhi Li <lizhi7(a)huaqin.corp-partner.google.com>
Change-Id: I15ab30f14df9dc02157009091aa8398e2fa75188
---
M src/mainboard/google/dedede/variants/baseboard/devicetree.cb
M src/mainboard/google/dedede/variants/sasukette/ramstage.c
2 files changed, 14 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/56804/11
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Ian Feng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56988 )
Change subject: mb/google/dedede/var/corori: Generate RAM ID and SPD file
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56988/comment/c5a67684_20136a57
PS1, Line 13:
> Maybe mention, that some generic file `lp4x-spd-1. […]
Done
File src/mainboard/google/dedede/variants/corori/memory/mem_parts_used.txt:
https://review.coreboot.org/c/coreboot/+/56988/comment/be5a1364_731ed6cc
PS1, Line 11: # Part Name
> Should this stay in the file?
Use gen_part_id.go tool to auto generate must be deleted.
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I'd like you to reexamine a change. Please visit
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Change subject: mb/google/dedede/var/corori: Generate RAM ID and SPD file
......................................................................
mb/google/dedede/var/corori: Generate RAM ID and SPD file
Add the support RAM parts for Corori.
Here is the ram part number list:
DRAM Part Name ID to assign
H9HCNNNBKMMLXR-NEE 0 (0000)
K4U6E3S4AA-MGCR 0 (0000)
lp4x-spd-1.hex # ID = 0(0b0000) Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR
BUG=b:196744958
BRANCH=keeby
TEST=emerge-keeby coreboot
Signed-off-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com>
Change-Id: Ia11b5db145deeea838a8f5949accdb11e13342f2
---
M src/mainboard/google/dedede/variants/corori/memory/Makefile.inc
M src/mainboard/google/dedede/variants/corori/memory/dram_id.generated.txt
M src/mainboard/google/dedede/variants/corori/memory/mem_parts_used.txt
3 files changed, 6 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/56988/2
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Change subject: drivers/wifi/generic: Enable DSM ACPI entries for Intel WIFI card
......................................................................
drivers/wifi/generic: Enable DSM ACPI entries for Intel WIFI card
Add support for DSM functions as per the document
559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf
BUG=b:191720858
TEST=Check the generated SSDT tables for DSM method
Change-Id: Ie154edf188531fe6c260274edaa694cf3b3605d3
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com>
---
M src/drivers/wifi/generic/acpi.c
M src/include/sar.h
M src/vendorcode/google/chromeos/sar.c
3 files changed, 166 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/56751/13
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