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Change subject: Revert "src/soc/intel/cannonlake: Update C-state latency control limits"
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Great, thanks for confirming!
Sorry for the silence from my side, I meant to comment here before some vacation
but it got lost. IIRC, there was an [RFC] tag initially, got dropped somehow, sorry.
Thanks Vaibhav, for the clarification! IMHO, the directory should be called
`cannonpoint` as that is what it was always meant and used for (all platforms
using this generation of PCH). Cannon Lake support was dropped because there
were no products with it.
I guess we can close this thread.
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Change subject: payloads/external/tianocore: Add build argument for 4G Decode
......................................................................
Patch Set 20:
(2 comments)
File payloads/external/tianocore/Kconfig:
https://review.coreboot.org/c/coreboot/+/56223/comment/cc4730b9_91c7aca8
PS16, Line 86: bool "Avoid above 4G memory"
: default n
: help
: Select this option to not reserve memory above 4G. This will allow
: the payload to use all of the memory.
> > How does it work if Above4GDecode() is not called? What is […]
The current version says this:
config TIANOCORE_ABOVE_4G_DECODE
bool "Enable above 4G memory"
That's two-times incosistent: 1. it uses the term `decode` which is not
related to what the option does. 2. it says `decode` in one line and `memory`
in the next. So I would just change it to `TIANOCORE_ABOVE_4G_MEMORY`.
No confusing `Decode` or `EFI` or `Compatibility` or `Mode` needed, why not
just name things by what they do?
File payloads/external/tianocore/Kconfig:
https://review.coreboot.org/c/coreboot/+/56223/comment/f06d1215_ed29bbe2
PS20, Line 92: reserve memory above 4G
I fear this was written after my misunderstanding of what is `reserved`.
Usually we reserve memory to make sure it's not used (for something else),
but it seems in this case memory is reserved for tianocore, so only the
reserved memory will be used. (I would call it allocation, actually.)
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Change subject: superio/smsc: Add support for the SCH555x series
......................................................................
Patch Set 12:
(7 comments)
File src/superio/smsc/sch5555/sch5555.h:
https://review.coreboot.org/c/coreboot/+/55250/comment/1ffaad86_72719742
PS1, Line 51: #define EMI_IOBASE 0xa00
: #define RUNTIME_IOBASE 0xa40
> Alright, I'll revisit if I get bored enough
Can't we set them as io resources in the devicetree? (and then read that in C code)
File src/superio/smsc/sch555x/bootblock.c:
https://review.coreboot.org/c/coreboot/+/55250/comment/35cfde8c_9e461541
PS12, Line 35: // Enable IRQs
Why?
(also, mixing comment styles is a little irritating)
File src/superio/smsc/sch555x/ramstage.c:
https://review.coreboot.org/c/coreboot/+/55250/comment/811b7014_9afea6c6
PS12, Line 1: ;;
w-what? :)
https://review.coreboot.org/c/coreboot/+/55250/comment/b47c79b5_64ca8bb6
PS12, Line 13: pc_keyboard_init(NO_AUX_DEVICE);
Why add untested code?
https://review.coreboot.org/c/coreboot/+/55250/comment/46a24cbb_29c37c2e
PS12, Line 74: 0x70
PNP_IDX_IRQ0
https://review.coreboot.org/c/coreboot/+/55250/comment/fbfd46a1_5d4c96f6
PS12, Line 77: 0x72
PNP_IDX_IRQ1
File src/superio/smsc/sch555x/sch555x.h:
PS12:
This file seems to mix internals and the mainboard API.
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Piotr Król has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50194 )
Change subject: util/liveiso: Add NixOS configs for bootable live systems
......................................................................
Patch Set 30:
(1 comment)
Patchset:
PS30:
Maciej, Michał, Krystian,
I would appreciate if you could take a look at this concept. Maybe this can be expanded or used in similar way as Dasharo Refrence OS. Maybe there is a way to join those concepts?
Best Regards,
Piotr
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Sugnan Prabhu S has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56750 )
Change subject: vc/google/chromeos: Add support for new SAR tables revisions
......................................................................
Patch Set 14:
(11 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56750/comment/10dfda9b_1c4b141f
PS12, Line 14: wdgs
> WGDS
Done
https://review.coreboot.org/c/coreboot/+/56750/comment/b5db8ed4_7b87e10d
PS12, Line 15: wdgs
> WGDS
Done
https://review.coreboot.org/c/coreboot/+/56750/comment/c03aefdb_afd3107e
PS12, Line 22: TEST=Checked the SSDT entries for WRDS, EWRD, WGDS and PPAG with
: different binaries generated by setting different versions in the
: config.star
> Does this mean you verified revisions 0, 1 and 2 are all generated and decoded correctly?
Yes it was verified with most of the combinations.
Patchset:
PS8:
> Hi Tim, […]
Ack
File src/drivers/wifi/generic/acpi.c:
https://review.coreboot.org/c/coreboot/+/56750/comment/6635e46f_eb07ddfd
PS12, Line 55: if (sar_table->version > 2) {
: printk(BIOS_ERR, "Invalid SAR table version: %x02\n", sar_table->version);
: return;
: }
> suggestion: move this to an `else` clause after line 75, e.g.: […]
Done
https://review.coreboot.org/c/coreboot/+/56750/comment/9b28a956_e0bb6e83
PS12, Line 141: wgds
> WGDS
Done
File src/include/sar.h:
https://review.coreboot.org/c/coreboot/+/56750/comment/be5b9760_a5036f7f
PS12, Line 7: #define NUM_SAR_LIMITS 4
: #define BYTES_PER_SAR_LIMIT 10
: #define BYTES_PER_SAR_LIMIT_REV1 22
: #define BYTES_PER_SAR_LIMIT_REV2 (BYTES_PER_SAR_LIMIT_REV1 * 2)
: #define ANT_GAINS_TABLE_COUNT 2
: #define REVISION_SIZE 1
: #define PPAG_MODE_SIZE 1
> nit: line these all up on the right side
Done
File src/vendorcode/google/chromeos/sar_v2.c:
PS12:
> Tim, […]
Ack
https://review.coreboot.org/c/coreboot/+/56750/comment/4bbd9ec9_dcd891a1
PS12, Line 14: if (sar_table->version == 0)
: return BYTES_PER_SAR_LIMIT * NUM_SAR_LIMITS + REVISION_SIZE;
: else if (sar_table->version == 1)
: return BYTES_PER_SAR_LIMIT_REV1 * NUM_SAR_LIMITS + REVISION_SIZE;
: else if (sar_table->version == 2)
: return BYTES_PER_SAR_LIMIT_REV2 * NUM_SAR_LIMITS + REVISION_SIZE;
: else
: return REVISION_SIZE;
> with above, e.g. […]
Done
https://review.coreboot.org/c/coreboot/+/56750/comment/836b5498_fdc12c08
PS12, Line 24: wgds_table_size
> similar here
Done
https://review.coreboot.org/c/coreboot/+/56750/comment/ccff4b61_4ada21ef
PS12, Line 34: antgains_table_size
> would just return `0` for USE_SAR
Done
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Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56750
to look at the new patch set (#15).
Change subject: vc/google/chromeos: Add support for new SAR tables revisions
......................................................................
vc/google/chromeos: Add support for new SAR tables revisions
Existing SAR infrastructure supports only revision 0 of the SAR tables.
This patch modifies it to extend support intel wifi 6 and wifi 6e
configs as per the connectivity document:
559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf
The SAR table and WGDS configuration blocks size with in the earlier
SAR binary was static with option to enable WGDS block dynamically
using a coreboot config. The new binary format can support to have any
block as dynamic and the size of the configuration block depends on the
revision of the entry. This patch also adds support for PPAG ACPI
entries related to antenna gains.
BUG=b:193665559
TEST=Checked the SSDT entries for WRDS, EWRD, WGDS and PPAG with
different binaries generated by setting different versions in the
config.star
Change-Id: I08c3f321938eba04e8bcff4d87cb215422715bb2
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com>
---
M src/drivers/wifi/generic/Kconfig
M src/drivers/wifi/generic/Makefile.inc
M src/drivers/wifi/generic/acpi.c
M src/include/sar.h
M src/vendorcode/google/chromeos/Makefile.inc
M src/vendorcode/google/chromeos/sar.c
6 files changed, 372 insertions(+), 84 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/56750/15
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Zhi7 Li has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56804 )
Change subject: mb/google/dedede/var/sasukette: Add fw_config probe for non-ext VR
......................................................................
Patch Set 11:
(1 comment)
File src/mainboard/google/dedede/variants/sasukette/ramstage.c:
https://review.coreboot.org/c/coreboot/+/56804/comment/3aa0cd22_324dda36
PS10, Line 7: EXT_VR
> dont capitalize in between. Keep them all small letters.
Done
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I'd like you to reexamine a change. Please visit
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Change subject: mb/google/dedede: add gooey variant
......................................................................
mb/google/dedede: add gooey variant
gooey is the same design as boten, and differs only in replacing Cr50
with discrete TPM.
BUG=b:193366710
TEST=FW_NAME=gooey emerge-keeby coreboot
Signed-off-by: stanley.wu <stanley1.wu(a)lcfc.corp-partner.google.com>
Change-Id: I2a54f872a7d5c0bee76a9e6e309613d9357b380b
---
M src/mainboard/google/dedede/Kconfig
M src/mainboard/google/dedede/Kconfig.name
A src/mainboard/google/dedede/variants/gooey/Makefile.inc
A src/mainboard/google/dedede/variants/gooey/gpio.c
A src/mainboard/google/dedede/variants/gooey/include/variant/ec.h
A src/mainboard/google/dedede/variants/gooey/include/variant/gpio.h
A src/mainboard/google/dedede/variants/gooey/memory/Makefile.inc
A src/mainboard/google/dedede/variants/gooey/memory/dram_id.generated.txt
A src/mainboard/google/dedede/variants/gooey/memory/mem_list_variant.txt
A src/mainboard/google/dedede/variants/gooey/overridetree.cb
A src/mainboard/google/dedede/variants/gooey/variant.c
11 files changed, 479 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/56858/10
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Hello Timofey Komarov, build bot (Jenkins), Nico Huber, Patrick Georgi, Patrick Rudolph, Maxim Polyakov, Paul Menzel, Thomas Heijligen, Edward O'Callaghan, Michael Niewöhner, Marcello Sylvester Bauer,
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Change subject: util/liveiso: Add NixOS configs for bootable live systems
......................................................................
util/liveiso: Add NixOS configs for bootable live systems
Add NixOS configurations for bootable live systems containing a set of
tools which might be useful for firmware development in general and for
working on coreboot.
There are two configurations provided. One for console-only and a
graphical one, which is mostly the same as the console image but it
comes with Gnome Shell as window manager and some graphical tools in
addition.
An image can be built using `build-console.sh`, respectively
`build-graphical.sh`. The resulting iso image can be found in
`result/iso/`.
The console image results in ~700MB, while the graphical one results in
~2GB.
Change-Id: Iaf49d198e99781434bd89d2a8a125a4988b77e1c
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M MAINTAINERS
A util/liveiso/.gitignore
A util/liveiso/build-console.sh
A util/liveiso/build-graphical.sh
A util/liveiso/common.nix
A util/liveiso/console.nix
A util/liveiso/description.md
A util/liveiso/graphical.nix
8 files changed, 255 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/50194/30
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