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Ricardo Quesada has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56986 )
Change subject: elog: Define constant for RW region name
......................................................................
Patch Set 2:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56986/comment/08b100d5_f33f18e4
PS1, Line 7: elog: define RW_ELOG constant
> Please be more specific by adding “region name”(?) somewhere. Maybe: […]
Done
https://review.coreboot.org/c/coreboot/+/56986/comment/e96c42a2_e90cf42f
PS1, Line 9: This CL indroduces the ELOG_RW_REGION_NAME.
: This constant replaced the hardcoded "RW_ELOG" value.
: This constant will be used also by elogtool (see CL in the commit
: chain).
> Please do not break lines after each sentence. (If so, please separate paragraphs by a blank line. […]
Done
Patchset:
PS2:
thanks. fixed.
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Hello build bot (Jenkins), Furquan Shaikh, Jack Rosenthal,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56986
to look at the new patch set (#2).
Change subject: elog: Define constant for RW region name
......................................................................
elog: Define constant for RW region name
This CL indroduces the ELOG_RW_REGION_NAME. This constant replaced the
hardcoded "RW_ELOG" value. This constant will be used also by elogtool
(see CL in the commit chain).
BUG=b:172210863
Change-Id: Ie8d31204e65fd67d52b0f8ced7b8c1ffdcf5b539
Signed-off-by: Ricardo Quesada <ricardoq(a)google.com>
---
M src/commonlib/bsd/include/commonlib/bsd/elog.h
M src/drivers/elog/elog.c
2 files changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/56986/2
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56989 )
Change subject: mb/google/brya: reduce RW_MRC_CACHE size to 64K
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
From what I can tell, the MRC save size is currently 69619 bytes ...
could you try building with `USE=fw_debug emerge-brya -j intel-adlfsp; FW_NAME=brya0 emerge-brya -j coreboot chromeos-bootimage` and then look for
`Restore data of size `
in the 2nd boot (when it is reloading MRC parameters from flash) and double check that I am reading this correctly?
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Chen Wisley has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56905 )
Change subject: mb/google/dedede/variant/drawcia:Include SPD for MT53E512M32D1NP-046 WT:B
......................................................................
Patch Set 2:
This change is ready for review.
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56854 )
Change subject: MAINTAINERS: add missing vendorcode/amd/fsp/cezanne directory
......................................................................
MAINTAINERS: add missing vendorcode/amd/fsp/cezanne directory
The Cezanne FSP headers are located in that directory, so add it to the
Cezanne SoC folders in the maintainers file.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I4f4894f0b01fa916492f57a730c62f29c5f7c796
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56854
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Raul Rangel <rrangel(a)chromium.org>
---
M MAINTAINERS
1 file changed, 1 insertion(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Raul Rangel: Looks good to me, approved
diff --git a/MAINTAINERS b/MAINTAINERS
index 6e76197..a6bacb2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -604,6 +604,7 @@
M: Raul E Rangel <rrangel(a)chromium.org>
S: Maintained
F: src/soc/amd/cezanne/
+F: src/vendorcode/amd/fsp/cezanne/
AMD common SoC code
M: Marshall Dawson <marshalldawson3rd(a)gmail.com>
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57000 )
Change subject: mb/google/brya: set tcc_offset value to 10
......................................................................
Patch Set 1: Code-Review+2
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Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56919 )
Change subject: soc/amd/common: Skip psp_verstage on S0i3 resume
......................................................................
Patch Set 4:
(3 comments)
File src/soc/amd/common/psp_verstage/psp_verstage.c:
https://review.coreboot.org/c/coreboot/+/56919/comment/4aa35b81_dcab10d4
PS3, Line 206: * Currently, we want to skip running verstage on all S0i3 resumes. This relies
> > code indent should use tabs where possible […]
Done
https://review.coreboot.org/c/coreboot/+/56919/comment/c11e7e87_2692dada
PS3, Line 208: * TODO: Remove when PSP no longer loads verstage on S0i3 resum
> Typo: resum -> resume
Done
https://review.coreboot.org/c/coreboot/+/56919/comment/d2757b3b_42f3807c
PS3, Line 209: * b:196400450
> Nit: This can be moved along with TODO i.e. […]
Done
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Karthik Ramasubramanian has uploaded a new patch set (#4) to the change originally created by Martin Roth. ( https://review.coreboot.org/c/coreboot/+/56919 )
Change subject: soc/amd/common: Skip psp_verstage on S0i3 resume
......................................................................
soc/amd/common: Skip psp_verstage on S0i3 resume
PSP_Verstage will take almost the entire time to run that
is allotted to S0i3 resume. Since coreboot isn't running,
the PSP needs to handle any security requirements. The long-
term plan is that the PSP won't even load psp_verstage on S0i3
resume, but when it is loaded, this makes sure we exit
immediately
BUG=b:177064859
TEST=Verify that PSP_verstage doesn't run on S0i3 resume
Signed-off-by: Martin Roth <martinroth(a)chromium.org>
Change-Id: Ia7b2560ff3d7621922ec4bc0e8793961f5d7550f
---
M src/soc/amd/common/psp_verstage/psp_verstage.c
1 file changed, 10 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/56919/4
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