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Hello Lance Zhao, build bot (Jenkins), Furquan Shaikh, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56459
to look at the new patch set (#6).
Change subject: acpigen: Add ability to auto-generate _DSM Function 0
......................................................................
acpigen: Add ability to auto-generate _DSM Function 0
Since the value returned by _DSM function 0 for a given UUID is trivial
to calculate, add the ability to do so to the
acpigen_write_dsm() functions.
Change-Id: Id9be050442485b42202cf91649aa94e56f35032a
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
---
M src/acpi/acpigen.c
M src/include/acpi/acpigen.h
2 files changed, 46 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/56459/6
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Change subject: [TESTONLY]prodive/hermes: Try to run UART2 in ACPI mode
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/common/block/uart/uart.c:
https://review.coreboot.org/c/coreboot/+/56461/comment/c3236f6a_cf199d57
PS2, Line 139: res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
> > | IORESOURCE_RESERVE is missing […]
it's required for non ACPI aware payloads like EDK2 and bootloader's like GRUB. I'm not aware that such software makes any use of the MMIO region, so this is more to satisfy the e820 spec.
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Change subject: soc/intel/alderlake: set default PL4 values for different SKUs
......................................................................
Patch Set 3: Code-Review+2
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Change subject: Revert "src/soc/intel/cannonlake: Update C-state latency control limits"
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56662/comment/f02ebe89_2a0025bc
PS1, Line 14:
> Michael, did you ever manage to achieve S0ix on your CML-U device?
Sorry for the delay, I just tested this on google/dratini (CML-U), and S0ix is still functional with this patch.
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Change subject: soc/amd/common/block/spi: Add SPI config to Kconfig
......................................................................
Patch Set 3:
(1 comment)
File src/soc/amd/common/block/spi/Kconfig:
https://review.coreboot.org/c/coreboot/+/56884/comment/a5e6df57_95bf57a6
PS3, Line 20: 0
> em100 can support 4 can't it?
HOLD line alone needs to be floating. Otherwise I believe it should support Dual mode.
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Change subject: [TESTONLY]prodive/hermes: Try to run UART2 in ACPI mode
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/common/block/uart/uart.c:
https://review.coreboot.org/c/coreboot/+/56461/comment/8d30c383_e73f6230
PS2, Line 120: 0xfe020000
> > 0xFE032000 […]
Apparently, FSP does this so that the SerialIO resources don't change across boots, because some OSes cache resource info. I think Windows reconfigures devices if resources change, which slows down boot significantly. Oh, and these BARs fall within the "PCH preserved range" mentioned elsewhere in soc/intel code.
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Change subject: soc/intel/common: Add TGL-H PCI IDs
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
File src/include/device/pci_ids.h:
https://review.coreboot.org/c/coreboot/+/56900/comment/06cbdf36_77f3e3b4
PS1, Line 3942: #define PCI_DEVICE_ID_INTEL_TGL_ID_H_4_1 0x9A16
> The value doesn't exist in the CPU EDS. […]
Ack
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Change subject: soc/intel/alderlake: Irms UPD enable
......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS7:
What is this for?
What kind of effect is this going to have on the VRs ?
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