Attention is currently required from: Jeremy Soller.
Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57055 )
Change subject: mb/system76/*: cmos.layout: Reserve century byte
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/system76/gaze15/cmos.layout:
https://review.coreboot.org/c/coreboot/+/57055/comment/8d278096_a8b56698
PS1, Line 12: 400 8 r 0 century
Would it be better to have this as a hex field rather than a reserved field?
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Change subject: amdfwtool: Detect the flag multilevel to decide the actual value
......................................................................
Patch Set 1:
(2 comments)
File util/amdfwtool/amdfwtool.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-126428):
https://review.coreboot.org/c/coreboot/+/57063/comment/ba3a17ef_6a2a48c2
PS1, Line 589: amd_cb_config *cb_config)
need consistent spacing around '*' (ctx:WxV)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-126428):
https://review.coreboot.org/c/coreboot/+/57063/comment/706fd52e_363569e5
PS1, Line 770: amd_cb_config *cb_config)
need consistent spacing around '*' (ctx:WxV)
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Hello Zheng Bao,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/57063
to review the following change.
Change subject: amdfwtool: Detect the flag multilevel to decide the actual value
......................................................................
amdfwtool: Detect the flag multilevel to decide the actual value
To save the space for FW, some of the FWs are going to be define as
LVL2 entries. To be compatible to "flattened" layout, we still drop
the LVL2 entry to level1 if there is only one level.
Change-Id: Ibe8cdd5c14225899352b02bb19aae6059d56d428
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M util/amdfwtool/amdfwtool.c
1 file changed, 16 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/57063/1
diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c
index 1c662be..8f9acf1 100644
--- a/util/amdfwtool/amdfwtool.c
+++ b/util/amdfwtool/amdfwtool.c
@@ -585,7 +585,8 @@
psp_directory_table *pspdir,
psp_directory_table *pspdir2,
amd_fw_entry *fw_table,
- uint32_t cookie)
+ uint32_t cookie,
+ amd_cb_config *cb_config)
{
ssize_t bytes;
unsigned int i, count;
@@ -598,7 +599,9 @@
* 1st-level cookie may indicate level 1 or flattened. If the caller
* passes a pointer to a 2nd-level table, then assume not flat.
*/
- if (cookie == PSPL2_COOKIE)
+ if (cb_config->multi_level == 0)
+ level = PSP_LVL1;
+ else if (cookie == PSPL2_COOKIE)
level = PSP_LVL2;
else if (pspdir2)
level = PSP_LVL1;
@@ -763,7 +766,8 @@
bios_directory_table *biosdir,
bios_directory_table *biosdir2,
amd_bios_entry *fw_table,
- uint32_t cookie)
+ uint32_t cookie,
+ amd_cb_config *cb_config)
{
ssize_t bytes;
unsigned int i, count;
@@ -779,7 +783,9 @@
* 1st-level cookie may indicate level 1 or flattened. If the caller
* passes a pointer to a 2nd-level table, then assume not flat.
*/
- if (cookie == BDT2_COOKIE)
+ if (cb_config->multi_level == 0)
+ level = BDT_LVL1;
+ else if (cookie == BDT2_COOKIE)
level = BDT_LVL2;
else if (biosdir2)
level = BDT_LVL1;
@@ -1564,16 +1570,16 @@
/* Do 2nd PSP directory followed by 1st */
psp_directory_table *pspdir2 = new_psp_dir(&ctx, cb_config.multi_level);
integrate_psp_firmwares(&ctx, pspdir2, 0,
- amd_psp_fw_table, PSPL2_COOKIE);
+ amd_psp_fw_table, PSPL2_COOKIE, &cb_config);
pspdir = new_psp_dir(&ctx, cb_config.multi_level);
integrate_psp_firmwares(&ctx, pspdir, pspdir2,
- amd_psp_fw_table, PSP_COOKIE);
+ amd_psp_fw_table, PSP_COOKIE, &cb_config);
} else {
/* flat: PSP 1 cookie and no pointer to 2nd table */
pspdir = new_psp_dir(&ctx, cb_config.multi_level);
integrate_psp_firmwares(&ctx, pspdir, 0,
- amd_psp_fw_table, PSP_COOKIE);
+ amd_psp_fw_table, PSP_COOKIE, &cb_config);
}
if (comboable)
@@ -1601,16 +1607,16 @@
bios_directory_table *biosdir2 =
new_bios_dir(&ctx, cb_config.multi_level);
integrate_bios_firmwares(&ctx, biosdir2, 0,
- amd_bios_table, BDT2_COOKIE);
+ amd_bios_table, BDT2_COOKIE, &cb_config);
biosdir = new_bios_dir(&ctx, cb_config.multi_level);
integrate_bios_firmwares(&ctx, biosdir, biosdir2,
- amd_bios_table, BDT1_COOKIE);
+ amd_bios_table, BDT1_COOKIE, &cb_config);
} else {
/* flat: BDT1 cookie and no pointer to 2nd table */
biosdir = new_bios_dir(&ctx, cb_config.multi_level);
integrate_bios_firmwares(&ctx, biosdir, 0,
- amd_bios_table, BDT1_COOKIE);
+ amd_bios_table, BDT1_COOKIE, &cb_config);
}
switch (soc_id) {
case PLATFORM_RENOIR:
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Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57051 )
Change subject: soc/amd/common/block/lpc,mb/google/guybrush: Use #defines for eSPI setup
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/guybrush/bootblock.c:
https://review.coreboot.org/c/coreboot/+/57051/comment/8dcf8290_8fe4676b
PS1, Line 51: dword = pci_read_config32(SOC_LPC_DEV, LPC_MISC_CONTROL_BITS);
: dword &= ~(LDRQ0_PD_EN | LDRQ0_EN | BIT(3));
: dword |= LDRQ0_PU_EN;
: pci_write_config32(SOC_LPC_DEV, LPC_MISC_CONTROL_BITS, dword);
:
: pci_write_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE, 0);
: pci_write_config32(SOC_LPC_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, 0);
:
: dword = pm_read32(0x90);
: dword |= 1 << 16;
: pm_write32(0x90, dword);
:
: dword = pm_read32(PM_ACPI_CONF);
: dword |= 3 << 10;
: pm_write32(PM_ACPI_CONF, dword);
> Since you are cleaning this up, I think this should be moved to SoC code. […]
I agree. That's part of b/183149183. I did this because we are debugging b/195570693 and was trying to understand what all the pieces were doing.
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Sugnan Prabhu S has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/57061 )
Change subject: vc/google/chromeos: Add support for wifi time average SAR config
......................................................................
vc/google/chromeos: Add support for wifi time average SAR config
Add support for the WTAS ACPI BIOS configuration table as per the
connectivity document:
559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf
Change-Id: I42cf3cba7974e6db0e05de30846ef103a15fd584
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com>
---
M src/drivers/wifi/generic/acpi.c
M src/include/sar.h
M src/vendorcode/google/chromeos/sar.c
3 files changed, 85 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/57061/2
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Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Rizwan Qureshi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56751
to look at the new patch set (#15).
Change subject: drivers/wifi/generic: Add support for DSM methods for intel wifi card
......................................................................
drivers/wifi/generic: Add support for DSM methods for intel wifi card
Add support for DSM methods as per the connectivity document
559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf
BUG=b:191720858
TEST=Check the generated SSDT tables for DSM methods
Change-Id: Ie154edf188531fe6c260274edaa694cf3b3605d3
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com>
---
M src/drivers/wifi/generic/acpi.c
M src/include/sar.h
M src/vendorcode/google/chromeos/sar.c
3 files changed, 167 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/56751/15
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Angel Pons has uploaded a new patch set (#15) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/49899 )
Change subject: soc/intel/*: Update microcode as specified for MP-init
......................................................................
soc/intel/*: Update microcode as specified for MP-init
Move second microcode update in init_one_cpu() and
per_cpu_smm_trigger() to the right place. This follows the BWGs
specification which sums up to:
* It must happen after SMM has been relocated
* It must happen after PRMRR has been set up
* It must happen before clearing MCEs
As it's not documented if/when microcodes are updated in FSP-S always
attempt to update microcode again.
Change-Id: Idf2b009ac9dd7cd462abe0f787f27b09feb6ec5b
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/cpu/intel/haswell/haswell_init.c
M src/cpu/intel/model_2065x/model_2065x_init.c
M src/cpu/intel/model_206ax/model_206ax_init.c
M src/soc/intel/alderlake/cpu.c
M src/soc/intel/apollolake/cpu.c
M src/soc/intel/baytrail/cpu.c
M src/soc/intel/braswell/cpu.c
M src/soc/intel/cannonlake/cpu.c
M src/soc/intel/common/block/cpu/mp_init.c
M src/soc/intel/elkhartlake/cpu.c
M src/soc/intel/icelake/cpu.c
M src/soc/intel/jasperlake/cpu.c
M src/soc/intel/skylake/cpu.c
M src/soc/intel/tigerlake/cpu.c
14 files changed, 113 insertions(+), 28 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/49899/15
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Tim Crawford has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/51103 )
Change subject: doc/mb/system76/lemp9: Link to external info
......................................................................
Abandoned
This info shows up on doc.coreboot.org, so keep it
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