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Boris Mittelberg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54724 )
Change subject: mb/google/brya: Add two sensors for DPTF functionality
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
Q: Do you plan to add "lower" thermal limits, at least on one sensor, so the fan would start spinning before 70C? Something like
```
[1] = {
.target = DPTF_TEMP_SENSOR_1,
.thresholds = {
TEMP_PCT(80, 90),
TEMP_PCT(75, 80),
TEMP_PCT(70, 70),
TEMP_PCT(50, 90),
TEMP_PCT(47, 69),
TEMP_PCT(45, 56),
TEMP_PCT(42, 46),
TEMP_PCT(39, 36),}
```
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Marc Jones has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56904 )
Change subject: include/bcd: move bcd code to commonlib/bsd/include
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS1:
> I think it's OK since as Ricardo mentions, this code existed in mosys under a BSD license before cor […]
Ack
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Douglas Anderson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57057 )
Change subject: WIP: Herobrine: Initialize Pen and HP i2c devices
......................................................................
Patch Set 1: Code-Review-1
(1 comment)
Patchset:
PS1:
Probably belongs in mainboard_init()?
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56990 )
Change subject: mb/google/zork: only enable RTD2141 when present
......................................................................
mb/google/zork: only enable RTD2141 when present
An MST hub is only present on some devices that are configured with a
particular daughterboard indicated by EC fw_config, so add a fw_config
probe that matches the USB daughterboard ID from CBI to only enable it
on devices where present, using variant-specific daughterboard IDs.
BUG=b:185862297
TEST=RTD2141 remains in ACPI tables on a berknip with Dali DB, and is
not present on the same system if probe is changed to enable it
for picasso DB.
BRANCH=zork
Change-Id: I4ada9b492ab221fa98350bf2faf27a23342f3a55
Signed-off-by: Peter Marheine <pmarheine(a)chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56990
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Sam McNally <sammc(a)google.com>
---
M src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
M src/mainboard/google/zork/variants/berknip/overridetree.cb
M src/mainboard/google/zork/variants/morphius/overridetree.cb
M src/mainboard/google/zork/variants/trembyle/overridetree.cb
M src/mainboard/google/zork/variants/woomax/overridetree.cb
5 files changed, 55 insertions(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Sam McNally: Looks good to me, approved
diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
index 8b1c68a..a475202 100644
--- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
+++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
@@ -1,4 +1,9 @@
# SPDX-License-Identifier: GPL-2.0-or-later
+
+fw_config
+ field USB_DAUGHTERBOARD 0 3 end
+end
+
chip soc/amd/picasso
# Set FADT Configuration
@@ -408,7 +413,8 @@
register "name" = ""MSTH""
register "uid" = "1"
register "desc" = ""Realtek RTD2141B""
- device i2c 4a on end
+ # Device presence is variant-specific
+ device i2c 4a alias db_mst off end
end
end
end
diff --git a/src/mainboard/google/zork/variants/berknip/overridetree.cb b/src/mainboard/google/zork/variants/berknip/overridetree.cb
index fe2eade..793be78 100644
--- a/src/mainboard/google/zork/variants/berknip/overridetree.cb
+++ b/src/mainboard/google/zork/variants/berknip/overridetree.cb
@@ -1,4 +1,12 @@
# SPDX-License-Identifier: GPL-2.0-or-later
+
+fw_config
+ field USB_DAUGHTERBOARD
+ option BERKNIP_DB_PICASSO 0
+ option BERKNIP_DB_DALI 1
+ end
+end
+
chip soc/amd/picasso
# Start : OPN Performance Configuration
@@ -171,4 +179,8 @@
end
end
+ device ref db_mst on
+ probe USB_DAUGHTERBOARD BERKNIP_DB_DALI
+ end
+
end # chip soc/amd/picasso
diff --git a/src/mainboard/google/zork/variants/morphius/overridetree.cb b/src/mainboard/google/zork/variants/morphius/overridetree.cb
index cfc9cb3..bb5e0e7 100644
--- a/src/mainboard/google/zork/variants/morphius/overridetree.cb
+++ b/src/mainboard/google/zork/variants/morphius/overridetree.cb
@@ -1,4 +1,12 @@
# SPDX-License-Identifier: GPL-2.0-or-later
+
+fw_config
+ field USB_DAUGHTERBOARD
+ option MORPHIUS_DB_PICASSO 0
+ option MORPHIUS_DB_DALI 1
+ end
+end
+
chip soc/amd/picasso
# Start : OPN Performance Configuration
@@ -136,4 +144,8 @@
end
end
+ device ref db_mst on
+ probe USB_DAUGHTERBOARD MORPHIUS_DB_DALI
+ end
+
end # chip soc/amd/picasso
diff --git a/src/mainboard/google/zork/variants/trembyle/overridetree.cb b/src/mainboard/google/zork/variants/trembyle/overridetree.cb
index a558aca..394b3bc 100644
--- a/src/mainboard/google/zork/variants/trembyle/overridetree.cb
+++ b/src/mainboard/google/zork/variants/trembyle/overridetree.cb
@@ -1,4 +1,13 @@
# SPDX-License-Identifier: GPL-2.0-or-later
+
+fw_config
+ field USB_DAUGHTERBOARD
+ option TREMBYLE_DB_PICASSO 0
+ option TREMBYLE_DB_DALI 1
+ option TREMBYLE_DB_DALI_HDMI 2
+ end
+end
+
chip soc/amd/picasso
# Start : OPN Performance Configuration
@@ -104,4 +113,8 @@
end
end
+ device ref db_mst on
+ probe USB_DAUGHTERBOARD TREMBYLE_DB_DALI_HDMI
+ end
+
end # chip soc/amd/picasso
diff --git a/src/mainboard/google/zork/variants/woomax/overridetree.cb b/src/mainboard/google/zork/variants/woomax/overridetree.cb
index 20d4783..82a060f 100644
--- a/src/mainboard/google/zork/variants/woomax/overridetree.cb
+++ b/src/mainboard/google/zork/variants/woomax/overridetree.cb
@@ -1,5 +1,12 @@
# SPDX-License-Identifier: GPL-2.0-or-later
+fw_config
+ field USB_DAUGHTERBOARD
+ option WOOMAX_DB_PICASSO 0
+ option WOOMAX_DB_DALI 1
+ end
+end
+
chip soc/amd/picasso
# Start : OPN Performance Configuration
@@ -110,4 +117,8 @@
end
end
+ device ref db_mst on
+ probe USB_DAUGHTERBOARD WOOMAX_DB_DALI
+ end
+
end # chip soc/amd/picasso
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56919 )
Change subject: soc/amd/common: Skip psp_verstage on S0i3 resume
......................................................................
soc/amd/common: Skip psp_verstage on S0i3 resume
PSP_Verstage will take almost the entire time to run that
is allotted to S0i3 resume. Since coreboot isn't running,
the PSP needs to handle any security requirements. The long-
term plan is that the PSP won't even load psp_verstage on S0i3
resume, but when it is loaded, this makes sure we exit
immediately
BUG=b:177064859
TEST=Verify that PSP_verstage doesn't run on S0i3 resume
Signed-off-by: Martin Roth <martinroth(a)chromium.org>
Change-Id: Ia7b2560ff3d7621922ec4bc0e8793961f5d7550f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56919
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Raul Rangel <rrangel(a)chromium.org>
---
M src/soc/amd/common/psp_verstage/psp_verstage.c
1 file changed, 10 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Raul Rangel: Looks good to me, approved
diff --git a/src/soc/amd/common/psp_verstage/psp_verstage.c b/src/soc/amd/common/psp_verstage/psp_verstage.c
index 5c59c4f..d223c94 100644
--- a/src/soc/amd/common/psp_verstage/psp_verstage.c
+++ b/src/soc/amd/common/psp_verstage/psp_verstage.c
@@ -200,6 +200,16 @@
{
uint32_t retval;
struct vb2_context *ctx = NULL;
+ uint32_t bootmode = 0;
+
+ /*
+ * Currently, we want to skip running verstage on all S0i3 resumes. This relies
+ * on an assumption that the PSP will be checksumming all of its components.
+ * TODO(b/196400450): Remove when PSP no longer loads verstage on S0i3 resume.
+ */
+ svc_get_boot_mode(&bootmode);
+ if (bootmode == PSP_BOOT_MODE_S0i3_RESUME)
+ svc_exit(0);
/*
* Do not use printk() before console_init()
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57051 )
Change subject: soc/amd/common/block/lpc,mb/google/guybrush: Use #defines for eSPI setup
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/guybrush/bootblock.c:
https://review.coreboot.org/c/coreboot/+/57051/comment/8cd08cee_4296635c
PS1, Line 51: dword = pci_read_config32(SOC_LPC_DEV, LPC_MISC_CONTROL_BITS);
: dword &= ~(LDRQ0_PD_EN | LDRQ0_EN | BIT(3));
: dword |= LDRQ0_PU_EN;
: pci_write_config32(SOC_LPC_DEV, LPC_MISC_CONTROL_BITS, dword);
:
: pci_write_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE, 0);
: pci_write_config32(SOC_LPC_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, 0);
:
: dword = pm_read32(0x90);
: dword |= 1 << 16;
: pm_write32(0x90, dword);
:
: dword = pm_read32(PM_ACPI_CONF);
: dword |= 3 << 10;
: pm_write32(PM_ACPI_CONF, dword);
> I agree. That's part of b/183149183. […]
I already started working on that one and probably have some local changes, but it got stalled a bit on the issue with the bit names. i was asked to prioritize working on another bug yesterday
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