coreboot-gerrit August 2021

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Change in coreboot[master]: soc/intel/*: Update microcode as specified for MP-init
by Subrata Banik (Code Review) 21 Aug '21

21 Aug '21

Attention is currently required from: Patrick Rudolph, Tim Wawrzynczak, Angel Pons, Michael Niewöhner, Andrey Petrov, Nathaniel L Desimone. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49899 ) Change subject: soc/intel/*: Update microcode as specified for MP-init ...................................................................... Patch Set 15: (1 comment) File src/soc/intel/alderlake/cpu.c: https://review.coreboot.org/c/coreboot/+/49899/comment/4be0aaee_01deeeb0 PS15, Line 73: intel_microcode_load_unlocked(microcode_patch); please take a look into https://review.coreboot.org/c/coreboot/+/48847, atleast I'm aware on ADL, the 2nd ucode loading process has some particular windows which would get meet inside FSP-S call, hence we are passing ucode pointer and allow FSP-S to load as part of MP feature programming hence, I would like to guard this call with !USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI if possible -- To view, visit https://review.coreboot.org/c/coreboot/+/49899 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf2b009ac9dd7cd462abe0f787f27b09feb6ec5b Gerrit-Change-Number: 49899 Gerrit-PatchSet: 15 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Comment-Date: Fri, 20 Aug 2021 18:44:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: qualcomm/sc7180: Switch to common MIPI panel library
by Julius Werner (Code Review) 21 Aug '21

21 Aug '21

Julius Werner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56966 ) Change subject: qualcomm/sc7180: Switch to common MIPI panel library ...................................................................... qualcomm/sc7180: Switch to common MIPI panel library This patch changes the sc7180 boards to use the new common MIPI panel framework, which allows more flexible initialization command packing and sharing panel definitions between boards. (I'm taking the lane count control back out again for now, since it seems we only ever want 4 for now anyway, and if we ever have a need for a different lane count it's not clear whether that should be a property of the board or the panel or both. Better to leave that decision until we have a real use case.) Also, the code was not written to deal with DCS commands that were not a length divisible by 4 (it would read over the end of the command buffer). The corresponding kernel driver seems to pad the command with 0xff instead, let's do the same here. (Also increase the maximum allowed command length to 256 bytes, as per Qualcomm's recommendation.) Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I78f6efbaa9da88a3574d5c6a51061e308412340e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56966 Reviewed-by: Shelley Chen <shchen(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/device/mipi/Kconfig M src/device/mipi/Makefile.inc A src/device/mipi/panel-VIS_RM69299.c M src/mainboard/google/trogdor/Kconfig M src/mainboard/google/trogdor/Makefile.inc M src/mainboard/google/trogdor/mainboard.c D src/mainboard/google/trogdor/panel_driver.c M src/soc/qualcomm/sc7180/display/dsi.c M src/soc/qualcomm/sc7180/include/soc/display/mipi_dsi.h D src/soc/qualcomm/sc7180/include/soc/display/panel.h 10 files changed, 142 insertions(+), 153 deletions(-) Approvals: build bot (Jenkins): Verified Shelley Chen: Looks good to me, approved diff --git a/src/device/mipi/Kconfig b/src/device/mipi/Kconfig index 0b05e46..72105e4 100644 --- a/src/device/mipi/Kconfig +++ b/src/device/mipi/Kconfig @@ -35,3 +35,6 @@ config MIPI_PANEL_STA_2081101QFH032011_53G bool + +config MIPI_PANEL_VIS_RM69299 + bool diff --git a/src/device/mipi/Makefile.inc b/src/device/mipi/Makefile.inc index cea7c3af..d58e838 100644 --- a/src/device/mipi/Makefile.inc +++ b/src/device/mipi/Makefile.inc @@ -20,6 +20,8 @@ panel-params-$(CONFIG_MIPI_PANEL_STA_2081101QFH032011_53G) += panel-STA_2081101QFH032011_53G +panel-params-$(CONFIG_MIPI_PANEL_VIS_RM69299) += panel-VIS_RM69299 + $(foreach params,$(panel-params-y), \ $(eval cbfs-files-y += $(params)) \ $(eval $(params)-file := $(params).c:struct) \ diff --git a/src/device/mipi/panel-VIS_RM69299.c b/src/device/mipi/panel-VIS_RM69299.c new file mode 100644 index 0000000..5fdea60 --- /dev/null +++ b/src/device/mipi/panel-VIS_RM69299.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mipi_panel.h> + +struct panel_serializable_data VIS_RM69299 = { + .edid = { + .ascii_string = "RM69299", + .manufacturer_name = "RM", + .panel_bits_per_color = 8, + .panel_bits_per_pixel = 24, + .mode = { + .pixel_clock = 158695, + .lvds_dual_channel = 0, + .refresh = 60, + .ha = 1080, .hbl = 64, .hso = 26, .hspw = 2, + .va = 2248, .vbl = 64, .vso = 56, .vspw = 4, + .phsync = '-', .pvsync = '-', + .x_mm = 74, .y_mm = 131, + }, + }, + .orientation = LB_FB_ORIENTATION_NORMAL, + .init = { + PANEL_DCS(0xFE, 0x00, 0x15, 0x80), + PANEL_DCS(0xc2, 0x08, 0x15, 0x80), + PANEL_DCS(0x35, 0x00, 0x15, 0x80), + PANEL_DCS(0x51, 0xff, 0x15, 0x80), + PANEL_DCS(0x11, 0x00, 0x05, 0x80), + PANEL_DELAY(150), + PANEL_DCS(0x29, 0x00, 0x05, 0x80), + PANEL_DELAY(50), + PANEL_END, + }, +}; diff --git a/src/mainboard/google/trogdor/Kconfig b/src/mainboard/google/trogdor/Kconfig index 08004d5..164c05f 100644 --- a/src/mainboard/google/trogdor/Kconfig +++ b/src/mainboard/google/trogdor/Kconfig @@ -15,6 +15,7 @@ config TROGDOR_HAS_MIPI_PANEL bool default n + select MIPI_PANEL_VIS_RM69299 config TROGDOR_HAS_FINGERPRINT bool diff --git a/src/mainboard/google/trogdor/Makefile.inc b/src/mainboard/google/trogdor/Makefile.inc index f42e147..9a71ea5 100644 --- a/src/mainboard/google/trogdor/Makefile.inc +++ b/src/mainboard/google/trogdor/Makefile.inc @@ -15,7 +15,6 @@ romstage-y += chromeos.c ramstage-y += mainboard.c -ramstage-y += panel_driver.c ifneq ($(CONFIG_BOARD_GOOGLE_BUBS),y) ramstage-y += reset.c endif diff --git a/src/mainboard/google/trogdor/mainboard.c b/src/mainboard/google/trogdor/mainboard.c index 96751fe..02a1f7d 100644 --- a/src/mainboard/google/trogdor/mainboard.c +++ b/src/mainboard/google/trogdor/mainboard.c @@ -1,11 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootmode.h> +#include <cbfs.h> #include <console/console.h> #include <delay.h> #include <device/device.h> #include <device/i2c_simple.h> +#include <device/mipi_panel.h> #include <drivers/ti/sn65dsi86bridge/sn65dsi86bridge.h> +#include <edid.h> #include <framebuffer_info.h> #include <soc/display/mipi_dsi.h> #include <soc/display/mdssreg.h> @@ -64,7 +67,7 @@ qupv3_se_fw_load_and_init(QUPV3_1_SE5, SE_PROTOCOL_I2C, MIXED); /* Codec I2C */ } -static void configure_display(void) +static void power_on_bridge(void) { printk(BIOS_INFO, "%s: Bridge gpio init\n", __func__); @@ -75,25 +78,38 @@ gpio_output(GPIO_EN_PP3300_DX_EDP, 1); } -static enum cb_err display_init(struct edid *edid, const struct panel_data *pinfo) +static struct panel_serializable_data *get_mipi_panel(void) { - uint32_t dsi_bpp = 24; - uint32_t lanes = pinfo ? pinfo->lanes : 4; + const char *cbfs_filename = "panel-VIS_RM69299"; - if (mdss_dsi_config(edid, lanes, dsi_bpp)) - return CB_ERR; - if (CONFIG(TROGDOR_HAS_MIPI_PANEL)) { - if (mdss_dsi_panel_initialize(pinfo)) - return CB_ERR; - } else { - sn65dsi86_bridge_configure(BRIDGE_BUS, BRIDGE_CHIP, edid, lanes, dsi_bpp); + struct panel_serializable_data *panel = cbfs_map(cbfs_filename, NULL); + if (!panel) { + printk(BIOS_ERR, "Could not find panel data for %s!\n", cbfs_filename); + return NULL; } - if (CONFIG(TROGDOR_HAS_BRIDGE_BACKLIGHT)) - sn65dsi86_backlight_enable(BRIDGE_BUS, BRIDGE_CHIP); + return panel; +} - mdp_dsi_video_config(edid); - mdss_dsi_video_mode_config(edid, dsi_bpp); +static enum cb_err display_init(struct panel_serializable_data *panel) +{ + uint32_t dsi_bpp = 24; + uint32_t lanes = 4; + + if (mdss_dsi_config(&panel->edid, lanes, dsi_bpp)) + return CB_ERR; + if (CONFIG(TROGDOR_HAS_MIPI_PANEL)) { + if (mdss_dsi_panel_initialize(panel->init)) + return CB_ERR; + } else { + sn65dsi86_bridge_configure(BRIDGE_BUS, BRIDGE_CHIP, &panel->edid, + lanes, dsi_bpp); + if (CONFIG(TROGDOR_HAS_BRIDGE_BACKLIGHT)) + sn65dsi86_backlight_enable(BRIDGE_BUS, BRIDGE_CHIP); + } + + mdp_dsi_video_config(&panel->edid); + mdss_dsi_video_mode_config(&panel->edid, dsi_bpp); mdp_dsi_video_on(); return CB_SUCCESS; @@ -101,28 +117,37 @@ static void display_startup(void) { - static struct edid ed; - enum dp_pll_clk_src ref_clk = SN65_SEL_19MHZ; - const struct panel_data *pinfo = NULL; + struct panel_serializable_data *panel = NULL; - if (display_init_required()) { - if (CONFIG(TROGDOR_HAS_MIPI_PANEL)) { - pinfo = get_panel_config(&ed); - } else { - i2c_init(QUPV3_0_SE2, I2C_SPEED_FAST); /* EDP Bridge I2C */ - configure_display(); - mdelay(250); /* Delay for the panel to be up */ - sn65dsi86_bridge_init(BRIDGE_BUS, BRIDGE_CHIP, ref_clk); - if (sn65dsi86_bridge_read_edid(BRIDGE_BUS, BRIDGE_CHIP, &ed) < 0) - return; - } - - printk(BIOS_INFO, "display init!\n"); - if (display_init(&ed, pinfo) == CB_SUCCESS) - fb_new_framebuffer_info_from_edid(&ed, (uintptr_t)0); - - } else + if (!display_init_required()) { printk(BIOS_INFO, "Skipping display init.\n"); + return; + } + + if (CONFIG(TROGDOR_HAS_MIPI_PANEL)) { + panel = get_mipi_panel(); + if (!panel) + return; + } else { + enum dp_pll_clk_src ref_clk = SN65_SEL_19MHZ; + static struct panel_serializable_data edp_panel = { + .orientation = LB_FB_ORIENTATION_NORMAL, + }; + i2c_init(QUPV3_0_SE2, I2C_SPEED_FAST); /* EDP Bridge I2C */ + power_on_bridge(); + mdelay(250); /* Delay for the panel to be up */ + sn65dsi86_bridge_init(BRIDGE_BUS, BRIDGE_CHIP, ref_clk); + if (sn65dsi86_bridge_read_edid(BRIDGE_BUS, BRIDGE_CHIP, &edp_panel.edid) < 0) + return; + panel = &edp_panel; + } + + printk(BIOS_INFO, "display init!\n"); + edid_set_framebuffer_bits_per_pixel(&panel->edid, 32, 0); + if (display_init(panel) == CB_SUCCESS) { + struct fb_info *info = fb_new_framebuffer_info_from_edid(&panel->edid, 0); + fb_set_orientation(info, panel->orientation); + } } static void mainboard_init(struct device *dev) diff --git a/src/mainboard/google/trogdor/panel_driver.c b/src/mainboard/google/trogdor/panel_driver.c deleted file mode 100644 index 5da0209..0000000 --- a/src/mainboard/google/trogdor/panel_driver.c +++ /dev/null @@ -1,45 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <edid.h> -#include <string.h> -#include <types.h> -#include <soc/display/mipi_dsi.h> -#include <soc/display/panel.h> - -struct mipi_dsi_cmd visionox_init_cmds[] = { - {{0xFE, 0x00, 0x15, 0x80}, 0x4, 0}, - {{0xc2, 0x08, 0x15, 0x80}, 0x4, 0}, - {{0x35, 0x00, 0x15, 0x80}, 0x4, 0}, - {{0x51, 0xff, 0x15, 0x80}, 0x4, 0}, - {{0x11, 0x00, 0x05, 0x80}, 0x4, 150000}, - {{0x29, 0x00, 0x05, 0x80}, 0x4, 50000}, -}; - -static const struct edid visionox_edid = { - .ascii_string = "RM69299", - .manufacturer_name = "RM", - .panel_bits_per_color = 8, - .panel_bits_per_pixel = 24, - .mode = { - .pixel_clock = 158695, - .lvds_dual_channel = 0, - .refresh = 60, - .ha = 1080, .hbl = 64, .hso = 26, .hspw = 2, - .va = 2248, .vbl = 64, .vso = 56, .vspw = 4, - .phsync = '-', .pvsync = '-', - .x_mm = 74, .y_mm = 131, - }, -}; - -const struct panel_data panel_info = { - .lanes = 4, - .init_cmd = visionox_init_cmds, - .init_cmd_count = 6, -}; - -const struct panel_data *get_panel_config(struct edid *edid) -{ - memcpy(edid, &visionox_edid, sizeof(struct edid)); - edid_set_framebuffer_bits_per_pixel(edid, 32, 0); - return &panel_info; -} diff --git a/src/soc/qualcomm/sc7180/display/dsi.c b/src/soc/qualcomm/sc7180/display/dsi.c index 2682008..e0aa0ef 100644 --- a/src/soc/qualcomm/sc7180/display/dsi.c +++ b/src/soc/qualcomm/sc7180/display/dsi.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <device/mipi_panel.h> #include <device/mmio.h> #include <console/console.h> #include <assert.h> @@ -9,7 +10,6 @@ #include <types.h> #include <string.h> #include <soc/display/mipi_dsi.h> -#include <soc/display/panel.h> #include <soc/display/mdssreg.h> #include <soc/display/dsi_phy.h> @@ -30,7 +30,7 @@ #define HS_TX_TO 0xEA60 #define TIMER_RESOLUTION 0x4 -#define DSI_PAYLOAD_BYTE_BOUND 8 +#define DSI_PAYLOAD_BYTE_BOUND 256 #define DSI_PAYLOAD_SIZE_ALIGN 4 #define DSI_CMD_DMA_TPG_EN BIT(1) #define DSI_TPG_DMA_FIFO_MODE BIT(2) @@ -210,57 +210,55 @@ return status; } -static int mdss_dsi_cmds_tx(struct mipi_dsi_cmd *cmds, int count) +static cb_err_t mdss_dsi_send_init_cmd(enum panel_init_cmd cmd, const u8 *body, u8 len) { - struct mipi_dsi_cmd *cm; uint8_t *pload = _dma_coherent; uint32_t size; + cb_err_t ret = CB_SUCCESS; int data = 0; - int ret = 0; uint32_t *bp = NULL; - cm = cmds; + /* This implementation only supports DCS commands (I think?). */ + assert(cmd == PANEL_CMD_DCS); - for (int i = 0; i < count; i++) { - /* The payload size has to be a multiple of 4 */ - size = ALIGN_UP(cm->size, DSI_PAYLOAD_SIZE_ALIGN); - assert(size < DSI_PAYLOAD_BYTE_BOUND); - memcpy(pload, (cm[i].payload), size); + /* The payload size has to be a multiple of 4 */ + memcpy(pload, body, len); + size = ALIGN_UP(len, DSI_PAYLOAD_SIZE_ALIGN); + memset(pload + len, 0xff, size - len); + assert(size < DSI_PAYLOAD_BYTE_BOUND); - bp = (uint32_t *)pload; + bp = (uint32_t *)pload; - /* Enable custom pattern stored in TPG DMA FIFO */ - data = DSI_CMD_DMA_PATTERN_SEL; + /* Enable custom pattern stored in TPG DMA FIFO */ + data = DSI_CMD_DMA_PATTERN_SEL; - /* select CMD_DMA_FIFO_MODE to 1 */ - data |= DSI_TPG_DMA_FIFO_MODE; - data |= DSI_CMD_DMA_TPG_EN; + /* select CMD_DMA_FIFO_MODE to 1 */ + data |= DSI_TPG_DMA_FIFO_MODE; + data |= DSI_CMD_DMA_TPG_EN; - write32(&dsi0->test_pattern_gen_ctrl, data); - for (int j = 0; j < size; j += 4) { - write32(&dsi0->test_pattern_gen_cmd_dma_init_val, *bp); - bp++; - } - - if ((size % 8) != 0) - write32(&dsi0->test_pattern_gen_cmd_dma_init_val, 0x0); - - write32(&dsi0->dma_cmd_length, size); - write32(&dsi0->cmd_mode_dma_sw_trigger, 0x1); - ret += mdss_dsi_cmd_dma_trigger_for_panel(); - - /* Reset the DMA TPG FIFO */ - write32(&dsi0->tpg_dma_fifo_reset, 0x1); - write32(&dsi0->tpg_dma_fifo_reset, 0x0); - - /* Disable CMD_DMA_TPG */ - write32(&dsi0->test_pattern_gen_ctrl, 0x0); - if (cm[i].delay_us) - udelay(cm[i].delay_us); - else - udelay(80); + write32(&dsi0->test_pattern_gen_ctrl, data); + for (int j = 0; j < size; j += 4) { + write32(&dsi0->test_pattern_gen_cmd_dma_init_val, *bp); + bp++; } + if ((size % 8) != 0) + write32(&dsi0->test_pattern_gen_cmd_dma_init_val, 0x0); + + write32(&dsi0->dma_cmd_length, size); + write32(&dsi0->cmd_mode_dma_sw_trigger, 0x1); + if (mdss_dsi_cmd_dma_trigger_for_panel()) + ret = CB_ERR; + + /* Reset the DMA TPG FIFO */ + write32(&dsi0->tpg_dma_fifo_reset, 0x1); + write32(&dsi0->tpg_dma_fifo_reset, 0x0); + + /* Disable CMD_DMA_TPG */ + write32(&dsi0->test_pattern_gen_ctrl, 0x0); + + udelay(80); + return ret; } @@ -274,22 +272,19 @@ write32(&dsi0->err_int_mask0, 0x13FF3BFF); } -int mdss_dsi_panel_initialize(const struct panel_data *pinfo) +cb_err_t mdss_dsi_panel_initialize(const u8 *init_cmds) { - int status = 0; uint32_t ctrl_mode = 0; - struct mipi_dsi_cmd *cmds; - assert((pinfo != NULL) && (pinfo->init_cmd != NULL)); - cmds = pinfo->init_cmd; + assert(init_cmds != NULL); ctrl_mode = read32(&dsi0->ctrl); /* Enable command mode before sending the commands */ write32(&dsi0->ctrl, ctrl_mode | 0x04); - status = mdss_dsi_cmds_tx(cmds, pinfo->init_cmd_count); + cb_err_t ret = mipi_panel_parse_init_commands(init_cmds, mdss_dsi_send_init_cmd); write32(&dsi0->ctrl, ctrl_mode); mdss_dsi_clear_intr(); - return status; + return ret; } diff --git a/src/soc/qualcomm/sc7180/include/soc/display/mipi_dsi.h b/src/soc/qualcomm/sc7180/include/soc/display/mipi_dsi.h index 3b3dc51..a7c9b6e 100644 --- a/src/soc/qualcomm/sc7180/include/soc/display/mipi_dsi.h +++ b/src/soc/qualcomm/sc7180/include/soc/display/mipi_dsi.h @@ -3,7 +3,6 @@ #ifndef _SOC_DISPLAY_MIPI_DSI_H_ #define _SOC_DISPLAY_MIPI_DSI_H_ -#include <soc/display/panel.h> /********************************************************** DSI register configuration options **********************************************************/ @@ -15,12 +14,6 @@ #define DSI_VIDEO_DST_FORMAT_RGB666_LOOSE 2 #define DSI_VIDEO_DST_FORMAT_RGB888 3 -struct mipi_dsi_cmd { - char payload[4]; - uint32_t size; - int delay_us; -}; - enum { DSI_VIDEO_MODE, DSI_CMD_MODE, @@ -29,6 +22,6 @@ enum cb_err mdss_dsi_config(struct edid *edid, uint32_t num_of_lanes, uint32_t bpp); void mdss_dsi_clock_config(void); void mdss_dsi_video_mode_config(struct edid *edid, uint32_t bpp); -int mdss_dsi_panel_initialize(const struct panel_data *pinfo); +cb_err_t mdss_dsi_panel_initialize(const u8 *init_cmds); #endif diff --git a/src/soc/qualcomm/sc7180/include/soc/display/panel.h b/src/soc/qualcomm/sc7180/include/soc/display/panel.h deleted file mode 100644 index 04a7a6a..0000000 --- a/src/soc/qualcomm/sc7180/include/soc/display/panel.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _PANEL_H_ -#define _PANEL_H_ - -#include <types.h> - -struct panel_data { - uint8_t lanes; - struct mipi_dsi_cmd *init_cmd; - uint32_t init_cmd_count; -}; - -void panel_power_on(void); -const struct panel_data *get_panel_config(struct edid *edid); - -#endif /*_PANEL_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/56966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78f6efbaa9da88a3574d5c6a51061e308412340e Gerrit-Change-Number: 56966 Gerrit-PatchSet: 10 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Vinod Polimera <vpolimer(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: HACK: Herobrine: Reinit TPM INT gpio after qclib executes
by mturney mturney (Code Review) 21 Aug '21

21 Aug '21

Attention is currently required from: Shelley Chen. mturney mturney has uploaded a new patch set (#2) to the change originally created by Shelley Chen. ( https://review.coreboot.org/c/coreboot/+/57025 ) Change subject: HACK: Herobrine: Reinit TPM INT gpio after qclib executes ...................................................................... HACK: Herobrine: Reinit TPM INT gpio after qclib executes Signed-off-by: Shelley Chen <shchen(a)google.com> Change-Id: I4c43d120ebb49800c82aec263ff8c215b60c5201 --- M src/soc/qualcomm/common/qclib.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/57025/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/57025 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c43d120ebb49800c82aec263ff8c215b60c5201 Gerrit-Change-Number: 57025 Gerrit-PatchSet: 2 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: HACK: Herobrine: Reinit TPM INT GPIO
by mturney mturney (Code Review) 21 Aug '21

21 Aug '21

Attention is currently required from: Shelley Chen. mturney mturney has uploaded a new patch set (#2) to the change originally created by Shelley Chen. ( https://review.coreboot.org/c/coreboot/+/57022 ) Change subject: HACK: Herobrine: Reinit TPM INT GPIO ...................................................................... HACK: Herobrine: Reinit TPM INT GPIO We noticed at some point after running the blobs that we started getting TPM communication errors and realized that some QC blob was reconfiguring this GPIO during execution. We haven't debugged to which blob actually does this, so basically reinitializing the TPM interrupt GPIO excessively to get around this issue for now. Signed-off-by: Shelley Chen <shchen(a)google.com> Change-Id: I30426cc0392a640fb6d3b1d0fafca7e9a67a76c3 --- M src/mainboard/google/herobrine/boardid.c M src/mainboard/google/herobrine/chromeos.c M src/mainboard/google/herobrine/mainboard.c 3 files changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/57022/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/57022 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30426cc0392a640fb6d3b1d0fafca7e9a67a76c3 Gerrit-Change-Number: 57022 Gerrit-PatchSet: 2 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: HACK: herobrine: Assert USB_HUB_LDO_EN HACK
by mturney mturney (Code Review) 21 Aug '21

21 Aug '21

Attention is currently required from: Ravi kumar, Sandeep Maheswaram, Sudheer Amrabadi, mturney mturney. mturney mturney has uploaded a new patch set (#21) to the change originally created by Ravi kumar. ( https://review.coreboot.org/c/coreboot/+/55378 ) Change subject: HACK: herobrine: Assert USB_HUB_LDO_EN HACK ...................................................................... HACK: herobrine: Assert USB_HUB_LDO_EN HACK Some herobrine variants have USB hub powered by discrete LDO that is controlled by GPIO_157. Assert the GPIO on boot. BUG=b:182963902 TEST=Validated on qualcomm sc7180 and sc7280 development board. Signed-off-by: Sandeep Maheswaram <sanm(a)codeaurora.org> Change-Id: Ia94e046f9eb0d3ce593f3445e0203a7391c14de2 --- M src/mainboard/google/herobrine/mainboard.c 1 file changed, 11 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/55378/21 -- To view, visit https://review.coreboot.org/c/coreboot/+/55378 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia94e046f9eb0d3ce593f3445e0203a7391c14de2 Gerrit-Change-Number: 55378 Gerrit-PatchSet: 21 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Sandeep Maheswaram <sanm(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Sandeep Maheswaram <sanm(a)codeaurora.org> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: google/herobrine: configure gpio to detect board ID.
by mturney mturney (Code Review) 21 Aug '21

21 Aug '21

Attention is currently required from: Ravi kumar, Sudheer Amrabadi, mturney mturney. mturney mturney has uploaded a new patch set (#4) to the change originally created by Ravi kumar. ( https://review.coreboot.org/c/coreboot/+/56642 ) Change subject: google/herobrine: configure gpio to detect board ID. ...................................................................... google/herobrine: configure gpio to detect board ID. read gpio value to get board ID. Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Change-Id: I6de2a7e7b11ecce8325e0fd44dc7221d73729390 --- M src/mainboard/google/herobrine/boardid.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/56642/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/56642 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6de2a7e7b11ecce8325e0fd44dc7221d73729390 Gerrit-Change-Number: 56642 Gerrit-PatchSet: 4 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src/mainboard/herobrine: Initialize SPI FW for EC and TPM
by mturney mturney (Code Review) 21 Aug '21

21 Aug '21

Attention is currently required from: Shelley Chen, Ravi kumar, mturney mturney, Sudheer Amrabadi, Julius Werner. mturney mturney has uploaded a new patch set (#63) to the change originally created by Ravi kumar. ( https://review.coreboot.org/c/coreboot/+/50581 ) Change subject: src/mainboard/herobrine: Initialize SPI FW for EC and TPM ...................................................................... src/mainboard/herobrine: Initialize SPI FW for EC and TPM Initialize SPI firmware for EC and H1/TPM instances. Load QUP FW in respective Serial Engines. BUG=b:182963902 TEST=Validated on qualcomm sc7280 developement board Change-Id: I8cbdd1d59a0166688d52d61646db1b6764879a7c Signed-off-by: Roja Rani Yarubandi <rojay(a)codeaurora.org> --- M src/mainboard/google/herobrine/Kconfig M src/mainboard/google/herobrine/board.h M src/mainboard/google/herobrine/bootblock.c M src/mainboard/google/herobrine/chromeos.c M src/soc/qualcomm/common/spi.c 5 files changed, 43 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/50581/63 -- To view, visit https://review.coreboot.org/c/coreboot/+/50581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8cbdd1d59a0166688d52d61646db1b6764879a7c Gerrit-Change-Number: 50581 Gerrit-PatchSet: 63 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rajesh Patil <rajpat(a)qualcomm.corp-partner.google.com> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: include/bcd: move bcd code to commonlib/bsd/include
by Furquan Shaikh (Code Review) 21 Aug '21

21 Aug '21

Attention is currently required from: Hung-Te Lin, Ricardo Quesada, Marc Jones, Jack Rosenthal, Paul Menzel, Julius Werner. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56904 ) Change subject: include/bcd: move bcd code to commonlib/bsd/include ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56904 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2eba82da35838799bcbcf38303de6bd53f7eb72 Gerrit-Change-Number: 56904 Gerrit-PatchSet: 4 Gerrit-Owner: Ricardo Quesada <ricardoq(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jack Rosenthal <jrosenth(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc.jones(a)amd.corp-partner.google.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Ricardo Quesada <ricardoq(a)google.com> Gerrit-Attention: Marc Jones <marc.jones(a)amd.corp-partner.google.com> Gerrit-Attention: Jack Rosenthal <jrosenth(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 20 Aug 2021 18:22:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: qualcomm/sc7180: Switch to common MIPI panel library
by Shelley Chen (Code Review) 21 Aug '21

21 Aug '21

Attention is currently required from: Vinod Polimera, Julius Werner. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56966 ) Change subject: qualcomm/sc7180: Switch to common MIPI panel library ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78f6efbaa9da88a3574d5c6a51061e308412340e Gerrit-Change-Number: 56966 Gerrit-PatchSet: 9 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Vinod Polimera <vpolimer(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Vinod Polimera <vpolimer(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 20 Aug 2021 18:19:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: qualcomm/sc7180: Switch to common MIPI panel library
by Julius Werner (Code Review) 21 Aug '21

21 Aug '21

Attention is currently required from: Vinod Polimera, Shelley Chen, Julius Werner. Julius Werner has removed a vote from this change. ( https://review.coreboot.org/c/coreboot/+/56966 ) Change subject: qualcomm/sc7180: Switch to common MIPI panel library ...................................................................... Removed Verified-1 by build bot (Jenkins) <no-reply(a)coreboot.org> -- To view, visit https://review.coreboot.org/c/coreboot/+/56966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78f6efbaa9da88a3574d5c6a51061e308412340e Gerrit-Change-Number: 56966 Gerrit-PatchSet: 9 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Vinod Polimera <vpolimer(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Vinod Polimera <vpolimer(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: deleteVote

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coreboot-gerrit August 2021