coreboot-gerrit August 2021

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Change in coreboot[master]: vc/google/chromeos: Add support for wifi time average SAR config
by Sugnan Prabhu S (Code Review) 20 Aug '21

20 Aug '21

Sugnan Prabhu S has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/57061 ) Change subject: vc/google/chromeos: Add support for wifi time average SAR config ...................................................................... vc/google/chromeos: Add support for wifi time average SAR config Add support for the WTAS ACPI BIOS configuration table as per the connectivity document: 559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf Change-Id: I42cf3cba7974e6db0e05de30846ef103a15fd584 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> --- M src/drivers/wifi/generic/acpi.c M src/include/sar.h M src/vendorcode/google/chromeos/sar.c 3 files changed, 85 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/57061/1 diff --git a/src/drivers/wifi/generic/acpi.c b/src/drivers/wifi/generic/acpi.c index 3449af3..1ff081d 100644 --- a/src/drivers/wifi/generic/acpi.c +++ b/src/drivers/wifi/generic/acpi.c @@ -399,6 +399,61 @@ acpigen_pop_len(); } +static void emit_wifi_sar_avg_table(struct wifi_sar_avg_table *wtas) +{ + int i; + size_t package_size = 1; + + if (wtas == NULL) + return; + + /* + * Name (WTAS, Package() { + * { + * Revision, + * Package() + * { + * DomainType, // 0x7:WiFi + * WifiTASSelection, // Enable/Disable the TAS feature + * WifiTASListEntries, // No. of blocked countries not approved by OEM to + * BlockedListEntry1, support this feature + * BlockedListEntry2, + * BlockedListEntry3, + * BlockedListEntry4, + * BlockedListEntry5, + * BlockedListEntry6, + * BlockedListEntry7, + * BlockedListEntry8, + * BlockedListEntry9, + * BlockedListEntry10, + * BlockedListEntry11, + * BlockedListEntry12, + * BlockedListEntry13, + * BlockedListEntry14, + * BlockedListEntry15, + * BlockedListEntry16, + * } + * }) + */ + if (wtas->version > MAX_SAR_AVG_VERSION) + return; + + package_size = MAX_BLACKLIST_ENTRY + 3; + + acpigen_write_name("WTAS"); + acpigen_write_package(2); + acpigen_write_dword(wtas->version); + acpigen_write_package(package_size); + acpigen_write_dword(DOMAIN_TYPE_WIFI); + acpigen_write_dword(wtas->tas_selection); + acpigen_write_dword(wtas->tas_list_size); + for (i = 0; i < MAX_BLACKLIST_ENTRY; i++) + acpigen_write_byte(wtas->black_list_entry[i]); + + acpigen_pop_len(); + acpigen_pop_len(); +} + static void emit_sar_acpi_structures(const struct device *dev) { struct wifi_sar_limits sar_limits; @@ -419,6 +474,7 @@ emit_wifi_sar_table(sar_limits.sar_table); emit_wifi_sar_delta_table(sar_limits.wgds); emit_wifi_antgain_table(sar_limits.ant_gains); + emit_wifi_sar_avg_table(sar_limits.wtas); wifi_write_dsm(sar_limits.dsm); diff --git a/src/include/sar.h b/src/include/sar.h index 71cb851..df3faf8 100644 --- a/src/include/sar.h +++ b/src/include/sar.h @@ -11,6 +11,8 @@ #define NUM_SAR_LIMITS 4 #define PPAG_MODE_SIZE 1 #define REVISION_SIZE 1 +#define MAX_SAR_AVG_VERSION UINT8_MAX +#define MAX_BLACKLIST_ENTRY 16 enum { SAR_FCC, @@ -90,11 +92,19 @@ uint32_t unni_4; }; +struct wifi_sar_avg_table { + uint16_t version; + uint8_t tas_selection; + uint8_t tas_list_size; + uint8_t black_list_entry[MAX_BLACKLIST_ENTRY]; +} __packed; + /* Wifi SAR limit table structure */ struct wifi_sar_limits { struct wifi_sar_table *sar_table; struct wifi_sar_delta_table *wgds; struct wifi_ant_table *ant_gains; + struct wifi_sar_avg_table *wtas; struct wifi_dsm *dsm; }; diff --git a/src/vendorcode/google/chromeos/sar.c b/src/vendorcode/google/chromeos/sar.c index 1100830..cb818e2 100644 --- a/src/vendorcode/google/chromeos/sar.c +++ b/src/vendorcode/google/chromeos/sar.c @@ -63,6 +63,17 @@ return REVISION_SIZE; } +static int sar_avg_table_size(struct wifi_sar_avg_table *sar_avg) +{ + if (CONFIG(USE_SAR)) + return 0; + + if (sar_avg->version > MAX_SAR_AVG_VERSION) + return sizeof(sar_avg->version); + + return sizeof(struct wifi_sar_avg_table); +} + static int dsm_size(void) { if (CONFIG(USE_SAR)) @@ -81,6 +92,7 @@ * SAR_REVISION[SAR_ENABLE,DSAR_ENABLE,DSAR_SET_NUM <WRDD><EWRD>] * WGDS_REVISION[WGDS_DATA] * PPAG_REVISION[MODE,PPAG_DATA] + * WTAS_REVISION[WTAS_DATA] * DSM_DATA * * The configuration data will always have the revision added in the file for each of the @@ -112,6 +124,11 @@ * [Antenna gain used for 6525-6705MHz frequency] version 1 and 2 * [Antenna gain used for 6705-6865MHz frequency] version 1 and 2 * [Antenna gain used for 6865-7105MHz frequency] version 1 and 2 + * + * [WTAS_DATA] = + * [Enable/disable the TAS feature] + * [Number of blocked countries that are not approved by the OEM to support this feature] + * [black_list_entry_<1-16>: ISO country code to block] */ int get_wifi_sar_limits(struct wifi_sar_limits *sar_limits) { @@ -187,6 +204,8 @@ if (CONFIG(USE_SAR_V2)) { sar_limits->ant_gains = (struct wifi_ant_table *)sar_ptr; sar_ptr += antgains_table_size(sar_limits->ant_gains); + sar_limits->wtas = (struct wifi_sar_avg_table *)sar_ptr; + sar_ptr += sar_avg_table_size(sar_limits->wtas); sar_limits->dsm = (struct wifi_dsm *)sar_ptr; } -- To view, visit https://review.coreboot.org/c/coreboot/+/57061 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42cf3cba7974e6db0e05de30846ef103a15fd584 Gerrit-Change-Number: 57061 Gerrit-PatchSet: 1 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: vc/google/chromeos: Add support for per-platform antenna gain
by Sugnan Prabhu S (Code Review) 20 Aug '21

20 Aug '21

Sugnan Prabhu S has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/57060 ) Change subject: vc/google/chromeos: Add support for per-platform antenna gain ...................................................................... vc/google/chromeos: Add support for per-platform antenna gain Add support for the PPAG ACPI BIOS configuration table as per the connectivity document: 559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf Change-Id: Ie8d25113feeeb4a4242cfd7d72a5091d2d5fb389 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> --- M src/drivers/wifi/generic/acpi.c M src/include/sar.h M src/vendorcode/google/chromeos/sar.c 3 files changed, 123 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/57060/1 diff --git a/src/drivers/wifi/generic/acpi.c b/src/drivers/wifi/generic/acpi.c index 2d2a1b0..7d8706c 100644 --- a/src/drivers/wifi/generic/acpi.c +++ b/src/drivers/wifi/generic/acpi.c @@ -199,6 +199,66 @@ acpigen_pop_len(); } +static void emit_wifi_antgain_table(struct wifi_ant_table *ant_gains) +{ + int i; + size_t package_size = 1; + + if (ant_gains == NULL) + return; + + /* + * Name ("PPAG", Package () { + * Revision, + * Package () { + * Domain Type, // 0x7:WiFi + * PPAG Mode, // Defines the mode of ANT_gain control to be used + * ANT_gain Table Chain A // Defines the ANT_gain in dBi for chain A + * ANT_gain Table Chain B // Defines the ANT_gain in dBi for chain B + * } + * }) + */ + if (ant_gains->version == 0) { + package_size = sizeof(ant_gains->gains_rev0) + 2; + } else if (ant_gains->version == 1 || ant_gains->version == 2) { + package_size = sizeof(ant_gains->gains_rev1) + 2; + } else { + printk(BIOS_ERR, "Invalid antenna gains version: %d\n", ant_gains->version); + return; + } + + acpigen_write_name("PPAG"); + acpigen_write_package(2); + acpigen_write_dword(ant_gains->version); + acpigen_write_package(package_size); + acpigen_write_dword(DOMAIN_TYPE_WIFI); + acpigen_write_dword(ant_gains->mode); + for (i = 0; i < ANT_GAINS_TABLE_COUNT; i++) { + if (ant_gains->version == 0) { + acpigen_write_byte(ant_gains->gains_rev0[i].ant_gain_2400); + acpigen_write_byte(ant_gains->gains_rev0[i].ant_gain_5150_5350); + acpigen_write_byte(ant_gains->gains_rev0[i].ant_gain_5350_5470); + acpigen_write_byte(ant_gains->gains_rev0[i].ant_gain_5470_5725); + acpigen_write_byte(ant_gains->gains_rev0[i].ant_gain_5725_5950); + } else if (ant_gains->version == 1 || ant_gains->version == 2) { + acpigen_write_byte(ant_gains->gains_rev1[i].ant_gain_2400); + acpigen_write_byte(ant_gains->gains_rev1[i].ant_gain_5150_5350); + acpigen_write_byte(ant_gains->gains_rev1[i].ant_gain_5350_5470); + acpigen_write_byte(ant_gains->gains_rev1[i].ant_gain_5470_5725); + acpigen_write_byte(ant_gains->gains_rev1[i].ant_gain_5725_5945); + acpigen_write_byte(ant_gains->gains_rev1[i].ant_gain_5945_6165); + acpigen_write_byte(ant_gains->gains_rev1[i].ant_gain_6165_6405); + acpigen_write_byte(ant_gains->gains_rev1[i].ant_gain_6405_6525); + acpigen_write_byte(ant_gains->gains_rev1[i].ant_gain_6525_6705); + acpigen_write_byte(ant_gains->gains_rev1[i].ant_gain_6705_6865); + acpigen_write_byte(ant_gains->gains_rev1[i].ant_gain_6865_7105); + } + } + + acpigen_pop_len(); + acpigen_pop_len(); +} + static void emit_sar_acpi_structures(const struct device *dev) { struct wifi_sar_limits sar_limits; @@ -218,6 +278,7 @@ emit_wifi_sar_table(sar_limits.sar_table); emit_wifi_sar_delta_table(sar_limits.wgds); + emit_wifi_antgain_table(sar_limits.ant_gains); free(sar_limits.sar_table); } diff --git a/src/include/sar.h b/src/include/sar.h index 36c05f3..eba5ed8 100644 --- a/src/include/sar.h +++ b/src/include/sar.h @@ -4,6 +4,7 @@ #include <stdint.h> +#define ANT_GAINS_TABLE_COUNT 2 #define BYTES_PER_SAR_LIMIT 10 #define BYTES_PER_SAR_LIMIT_REV1 22 #define BYTES_PER_SAR_LIMIT_REV2 (BYTES_PER_SAR_LIMIT_REV1 * 2) @@ -18,6 +19,33 @@ SAR_NUM_WGDS_GROUPS }; +struct wifi_ant_table { + uint8_t version; + uint8_t mode; + union { + struct { + uint8_t ant_gain_2400; + uint8_t ant_gain_5150_5350; + uint8_t ant_gain_5350_5470; + uint8_t ant_gain_5470_5725; + uint8_t ant_gain_5725_5950; + } __packed gains_rev0[ANT_GAINS_TABLE_COUNT]; + struct { + uint8_t ant_gain_2400; + uint8_t ant_gain_5150_5350; + uint8_t ant_gain_5350_5470; + uint8_t ant_gain_5470_5725; + uint8_t ant_gain_5725_5945; + uint8_t ant_gain_5945_6165; + uint8_t ant_gain_6165_6405; + uint8_t ant_gain_6405_6525; + uint8_t ant_gain_6525_6705; + uint8_t ant_gain_6705_6865; + uint8_t ant_gain_6865_7105; + } __packed gains_rev1[ANT_GAINS_TABLE_COUNT]; + } __packed; +} __packed; + struct wifi_sar_delta_table { uint8_t version; union { @@ -55,6 +83,7 @@ struct wifi_sar_limits { struct wifi_sar_table *sar_table; struct wifi_sar_delta_table *wgds; + struct wifi_ant_table *ant_gains; }; /* diff --git a/src/vendorcode/google/chromeos/sar.c b/src/vendorcode/google/chromeos/sar.c index c4ad1fe..391e68b 100644 --- a/src/vendorcode/google/chromeos/sar.c +++ b/src/vendorcode/google/chromeos/sar.c @@ -50,6 +50,19 @@ return REVISION_SIZE; } +static int antgains_table_size(struct wifi_ant_table *gains_table) +{ + if (CONFIG(USE_SAR)) + return 0; + + if (gains_table->version == 0) + return sizeof(gains_table->gains_rev0) + REVISION_SIZE + PPAG_MODE_SIZE; + else if (gains_table->version == 1 || gains_table->version == 2) + return sizeof(gains_table->gains_rev1) + REVISION_SIZE + PPAG_MODE_SIZE; + else + return REVISION_SIZE; +} + /* * Retrieve WiFi SAR limits data from CBFS and decode it * Legacy WiFi SAR data is expected in the format: [<WRDD><EWRD>][WGDS] @@ -60,6 +73,7 @@ * SAR V2 configuration data is expected in the format: * SAR_REVISION[SAR_ENABLE,DSAR_ENABLE,DSAR_SET_NUM <WRDD><EWRD>] * WGDS_REVISION[WGDS_DATA] + * PPAG_REVISION[MODE,PPAG_DATA] * * The configuration data will always have the revision added in the file for each of the * block, based on the revision number and validity, size of the specific block will be @@ -75,6 +89,21 @@ * [GROUP#0] is for FCC * [GROUP#1] is for Europe/Japan * [GROUP#2] is for ROW + * + * [PPAG_DATA] = [ANT_gain Table Chain A] [ANT_gain Table Chain A] + * + * [ANT_gain Table] = + * [Antenna gain used for 2400MHz frequency] + * [Antenna gain used for 5150-5350MHz frequency] + * [Antenna gain used for 5350-5470MHz frequency] + * [Antenna gain used for 5470-5725MHz frequency] + * [Antenna gain used for 5725-5945MHz frequency] + * [Antenna gain used for 5945-6165MHz frequency] version 1 and 2 + * [Antenna gain used for 6165-6405MHz frequency] version 1 and 2 + * [Antenna gain used for 6405-6525MHz frequency] version 1 and 2 + * [Antenna gain used for 6525-6705MHz frequency] version 1 and 2 + * [Antenna gain used for 6705-6865MHz frequency] version 1 and 2 + * [Antenna gain used for 6865-7105MHz frequency] version 1 and 2 */ int get_wifi_sar_limits(struct wifi_sar_limits *sar_limits) { @@ -147,9 +176,12 @@ sar_limits->wgds = (struct wifi_sar_delta_table *)sar_ptr; sar_ptr += wgds_table_size(sar_limits->wgds); + if (CONFIG(USE_SAR_V2)) + sar_limits->ant_gains = (struct wifi_ant_table *)sar_ptr; expected_sar_bin_len = sar_table_size(sar_limits->sar_table) + - wgds_table_size(sar_limits->wgds); + wgds_table_size(sar_limits->wgds) + + antgains_table_size(sar_limits->ant_gains); if (sar_bin_len != expected_sar_bin_len) { printk(BIOS_ERR, "Error: length mismatch: expected: %ld, obtained: %ld\n", expected_sar_bin_len, sar_bin_len); -- To view, visit https://review.coreboot.org/c/coreboot/+/57060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8d25113feeeb4a4242cfd7d72a5091d2d5fb389 Gerrit-Change-Number: 57060 Gerrit-PatchSet: 1 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/wifi/generic: Enable DSM ACPI entries for Intel WIFI card
by Sugnan Prabhu S (Code Review) 20 Aug '21

20 Aug '21

Attention is currently required from: Furquan Shaikh, Paul Menzel, Tim Wawrzynczak, Rizwan Qureshi. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Rizwan Qureshi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56751 to look at the new patch set (#14). Change subject: drivers/wifi/generic: Enable DSM ACPI entries for Intel WIFI card ...................................................................... drivers/wifi/generic: Enable DSM ACPI entries for Intel WIFI card Add support for DSM methods as per the connectivity document 559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf BUG=b:191720858 TEST=Check the generated SSDT tables for DSM methods Change-Id: Ie154edf188531fe6c260274edaa694cf3b3605d3 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> --- M src/drivers/wifi/generic/acpi.c M src/include/sar.h M src/vendorcode/google/chromeos/sar.c 3 files changed, 167 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/56751/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/56751 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie154edf188531fe6c260274edaa694cf3b3605d3 Gerrit-Change-Number: 56751 Gerrit-PatchSet: 14 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie.chen(a)intel.com> Gerrit-CC: Janiex Tu <janiex.tu(a)intel.corp-partner.google.com> Gerrit-CC: Matt Chen <matt.chen(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sherry An <sherry.an(a)intel.com> Gerrit-CC: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: vc/google/chromeos: Add support for new SAR tables revisions
by Sugnan Prabhu S (Code Review) 20 Aug '21

20 Aug '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Paul Menzel. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56750 to look at the new patch set (#17). Change subject: vc/google/chromeos: Add support for new SAR tables revisions ...................................................................... vc/google/chromeos: Add support for new SAR tables revisions Existing SAR infrastructure supports only revision 0 of the SAR tables. This patch modifies it to extend support for intel wifi 6 and wifi 6e configurations as per the connectivity document: 559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf The SAR table and WGDS configuration block sizes were static in the previous SAR binary format. In the new binary format every configuration block starts with a revision and the following block size is calculated based on it, which also supports enabling/disabling a configuration block by setting the revision to invalid. BUG=b:193665559 TEST=Checked the SSDT entries for WRDS, EWRD and WGDS with different binaries generated by setting different versions in the config.star Change-Id: I08c3f321938eba04e8bcff4d87cb215422715bb2 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> --- M src/drivers/wifi/generic/Kconfig M src/drivers/wifi/generic/Makefile.inc M src/drivers/wifi/generic/acpi.c M src/include/sar.h M src/vendorcode/google/chromeos/Makefile.inc M src/vendorcode/google/chromeos/sar.c 6 files changed, 273 insertions(+), 104 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/56750/17 -- To view, visit https://review.coreboot.org/c/coreboot/+/56750 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08c3f321938eba04e8bcff4d87cb215422715bb2 Gerrit-Change-Number: 56750 Gerrit-PatchSet: 17 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie.chen(a)intel.com> Gerrit-CC: Janiex Tu <janiex.tu(a)intel.corp-partner.google.com> Gerrit-CC: Matt Chen <matt.chen(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/tigerlake: Add PCH-H chipset devicetree
by Tim Crawford (Code Review) 20 Aug '21

20 Aug '21

Attention is currently required from: Jeremy Soller. Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56945 ) Change subject: soc/intel/tigerlake: Add PCH-H chipset devicetree ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/56945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc130461edcecc4a3e1f6544ccb905608881d2f7 Gerrit-Change-Number: 56945 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Comment-Date: Fri, 20 Aug 2021 13:24:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Add TGL-H power limits
by Tim Crawford (Code Review) 20 Aug '21

20 Aug '21

Attention is currently required from: Jeremy Soller. Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56943 ) Change subject: soc/intel/tigerlake: Add TGL-H power limits ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/56943 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6fa7c7338b3157b29ff72769238597e3c528aedb Gerrit-Change-Number: 56943 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Comment-Date: Fri, 20 Aug 2021 13:24:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: Add TGL-H CPUID
by Tim Crawford (Code Review) 20 Aug '21

20 Aug '21

Attention is currently required from: Jeremy Soller. Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56942 ) Change subject: soc/intel: Add TGL-H CPUID ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/56942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a76bcbd6661648a9284d683eb360ec956a9f9a6 Gerrit-Change-Number: 56942 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Comment-Date: Fri, 20 Aug 2021 13:24:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: tests: Add lib/cbfs-lookup-test test case
by Jakub Czapiga (Code Review) 20 Aug '21

20 Aug '21

Attention is currently required from: Julius Werner, Jan Dabros. Hello build bot (Jenkins), Julius Werner, Jan Dabros, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56813 to look at the new patch set (#7). Change subject: tests: Add lib/cbfs-lookup-test test case ...................................................................... tests: Add lib/cbfs-lookup-test test case Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: I2ebebba1468c19661741de8a8456605b1c5f56b6 --- M tests/lib/Makefile.inc A tests/lib/cbfs-lookup-test.c 2 files changed, 940 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/56813/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/56813 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ebebba1468c19661741de8a8456605b1c5f56b6 Gerrit-Change-Number: 56813 Gerrit-PatchSet: 7 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Jan Dabros <jsd(a)semihalf.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/variants/gimble: Correct I2C slave address and update ...
by Mark Hsieh (Code Review) 20 Aug '21

20 Aug '21

Attention is currently required from: YH Lin, Furquan Shaikh, Tim Wawrzynczak, Paul Fagerburg. Mark Hsieh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57059 ) Change subject: mb/google/brya/variants/gimble: Correct I2C slave address and update gpio.c ...................................................................... Patch Set 1: Code-Review+1 This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/57059 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf8adf2ed8dda9ae6da06e7e995bef9395cdee35 Gerrit-Change-Number: 57059 Gerrit-PatchSet: 1 Gerrit-Owner: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Comment-Date: Fri, 20 Aug 2021 09:04:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/galtic: modify touchscreen to native I2C protocol
by Paul Menzel (Code Review) 20 Aug '21

20 Aug '21

Attention is currently required from: Henry Sun, Frank Chu, Karthik Ramasubramanian. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57011 ) Change subject: mb/google/dedede/var/galtic: modify touchscreen to native I2C protocol ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/57011/comment/e92e2401_78391871 PS2, Line 8: Please describe the problem. -- To view, visit https://review.coreboot.org/c/coreboot/+/57011 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9e0fe726854d0128ad1bb430544640dc8f034ac Gerrit-Change-Number: 57011 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 20 Aug 2021 08:59:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit August 2021