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Change subject: vc/mediatek/mt8195: Enable DRAM Vcore DVFS settings
......................................................................
Patch Set 4:
(1 comment)
File src/vendorcode/mediatek/mt8195/dramc/dramc_top.c:
https://review.coreboot.org/c/coreboot/+/56106/comment/8809858b_2443c4df
PS3, Line 355: #elif CONFIG(CHROMEOS)
> I think the 'CHROMEOS' flag is used more like 'settings for Chromebook' - since there were comments […]
Done
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Hello Hung-Te Lin, build bot (Jenkins), Ryan Chuang, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56106
to look at the new patch set (#4).
Change subject: vc/mediatek/mt8195: Enable DRAM Vcore DVFS settings
......................................................................
vc/mediatek/mt8195: Enable DRAM Vcore DVFS settings
Signed-off-by: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com>
Change-Id: I39342aea902a87cdc2c5b862e5d1a889fcc822c5
---
M src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c
M src/vendorcode/mediatek/mt8195/dramc/dramc_top.c
2 files changed, 14 insertions(+), 24 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/56106/4
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Change subject: vc/mediatek/mt8195: Enable DRAM Vcore DVFS settings
......................................................................
Removed Code-Review+2 by Yu-Ping Wu <yupingso(a)google.com>
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Change subject: mb/google/dedede/var/galtic: Add charger throttling function
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/54673/comment/e0ba8367_a8e75be5
PS5, Line 10:
> Please document, where you got the values from.
check DAC register of RAA489000-Datasheet and co-work with intel james by mail,
=> control charger index * 64 = XX mA
32*64=2048
28*64=1792
24*64=1536
20*64=1280
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Change subject: spi: Limit the SPI NOR size
......................................................................
Patch Set 8:
(1 comment)
Patchset:
PS1:
> Hi Julius, […]
We can use a separate depthcharge build target (e.g. board/senor/defconfig instead of board/herobrine/defconfig) so you can increase the heap size if that's what's necessary. Talk to Philip or Bob if you want that set up.
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Change subject: vc/mediatek/mt8195: Enable DRAM Vcore DVFS settings
......................................................................
Patch Set 3:
(1 comment)
File src/vendorcode/mediatek/mt8195/dramc/dramc_top.c:
https://review.coreboot.org/c/coreboot/+/56106/comment/71bf4697_381fcca4
PS3, Line 355: #elif CONFIG(CHROMEOS)
> How is this ChromeOS specific?
I think the 'CHROMEOS' flag is used more like 'settings for Chromebook' - since there were comments [FOR CHROMEOS].
But it's true using CONFIG(CHROMEOS) here is not a good idea since the config in coreboot has a more specific meaning - build particular firmware (with vboot etc) for Chrome OS, not just Chromebooks.
@Rex can you change these (also the other configs in same file) to
#else // [FOR CHROMEOS / COREBOOT]
return ....
#endif
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Change subject: commonlib/bsd/future: Introduce future API
......................................................................
Patch Set 3: Code-Review-1
(1 comment)
Patchset:
PS3:
I still think that this is fundamentally the wrong parallelization model for coreboot, and that we should try to focus on one model rather than implementing a bunch of different options. Let's try to find a general consensus of which direction we want to go on the mailing list (https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/WBQ7…) before we start checking any patches in.
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