coreboot-gerrit July 2021

coreboot-gerrit@coreboot.org

1 participants
5824 discussions

Change in coreboot[master]: soc/intel/alderlake: Add GFx Device ID 0x46a6
by Tim Wawrzynczak (Code Review) 08 Jul '21

08 Jul '21

Attention is currently required from: Maulik V Vaghela, Paul Menzel, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56026 ) Change subject: soc/intel/alderlake: Add GFx Device ID 0x46a6 ...................................................................... Patch Set 1: (1 comment) File src/include/device/pci_ids.h: https://review.coreboot.org/c/coreboot/+/56026/comment/03b2c2c6_54ec7019 PS1, Line 3821: #define PCI_DEVICE_ID_INTEL_ADL_P_GT2_6 0x46a6 > Sorry Paul, this might interfere with order of Macros. […] They're already in an arbitrary order, that sounds like it should be a separate commit. -- To view, visit https://review.coreboot.org/c/coreboot/+/56026 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ca875c7faf2997d207aff9e292f94a3b6311e94 Gerrit-Change-Number: 56026 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 07 Jul 2021 22:27:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: cannonlake mainboards: Set PMC as hidden in devicetree
by Tim Wawrzynczak (Code Review) 08 Jul '21

08 Jul '21

Attention is currently required from: Furquan Shaikh, Matt DeVillier, Jeremy Soller, Angel Pons, Karthik Ramasubramanian. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56008 ) Change subject: cannonlake mainboards: Set PMC as hidden in devicetree ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > I wonder if we should set it for P2SB, too, then ``` src/mainboard/ocp/tiogapass/devicetree.cb: device pci 1f.1 hidden end # p2sb ``` tiogapass apparently does! The purpose would be if you have device callbacks you still want for the P2SB even though it's not enumerated -- To view, visit https://review.coreboot.org/c/coreboot/+/56008 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4a20ce9075ce7653388a5d3e281fe774bf89355 Gerrit-Change-Number: 56008 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 07 Jul 2021 22:19:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel: Fix microcode loading
by Tim Wawrzynczak (Code Review) 08 Jul '21

08 Jul '21

Attention is currently required from: Stefan Ott, Paul Menzel, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56153 ) Change subject: soc/intel: Fix microcode loading ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Thanks Nico and Stefan! -- To view, visit https://review.coreboot.org/c/coreboot/+/56153 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62def8014fd3f3bbf607b4d58ddc4dca4c695622 Gerrit-Change-Number: 56153 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 07 Jul 2021 22:10:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel: Fix microcode loading
by Tim Wawrzynczak (Code Review) 08 Jul '21

08 Jul '21

Attention is currently required from: Stefan Ott, Paul Menzel, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56153 ) Change subject: soc/intel: Fix microcode loading ...................................................................... Patch Set 2: (1 comment) Patchset: PS1: > Can you please add a Resolves: tag to the commit message? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/56153 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62def8014fd3f3bbf607b4d58ddc4dca4c695622 Gerrit-Change-Number: 56153 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 07 Jul 2021 22:09:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Stefan Ott <coreboot(a)desire.ch> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel: Fix microcode loading
by Tim Wawrzynczak (Code Review) 08 Jul '21

08 Jul '21

Attention is currently required from: Stefan Ott, Tim Wawrzynczak, Patrick Rudolph. Hello Stefan Ott, build bot (Jenkins), Nico Huber, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56153 to look at the new patch set (#2). Change subject: soc/intel: Fix microcode loading ...................................................................... soc/intel: Fix microcode loading Commit 1aa60a95bd8363d2 broke microcode loading for chipsets that have a microcode blob with a total_size field set to 0. This appears to be support for older chipsets, where the size was set to 0 and assumed to be 2048 bytes. The fix is to change the result of the subtraction to a signed type, and ensure the following comparison is done without promoting the signed type to an unsigned one. Resolves: https://ticket.coreboot.org/issues/313 Change-Id: I62def8014fd3f3bbf607b4d58ddc4dca4c695622 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/cpu/intel/microcode/microcode.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/56153/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56153 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62def8014fd3f3bbf607b4d58ddc4dca4c695622 Gerrit-Change-Number: 56153 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: sb/intel/common: Hide IFD options if !HAVE_IFD_BIN
by Tim Wawrzynczak (Code Review) 08 Jul '21

08 Jul '21

Attention is currently required from: Nico Huber, Angel Pons, Arthur Heymans, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56107 ) Change subject: sb/intel/common: Hide IFD options if !HAVE_IFD_BIN ...................................................................... Patch Set 1: (1 comment) File src/southbridge/intel/common/firmware/Kconfig: https://review.coreboot.org/c/coreboot/+/56107/comment/9979865a_11411d08 PS1, Line 27: config HAVE_ME_BIN : bool "Add Intel ME/TXE firmware" : depends on HAVE_IFD_BIN : help : The Intel processor in the selected system requires a special firmware : for an integrated controller. This might be called the Management : Engine (ME), the Trusted Execution Engine (TXE) or something else : depending on the chip. This firmware might or might not be available : in coreboot's 3rdparty/blobs repository. If it is not and if you don't : have access to the firmware from elsewhere, you can still build : coreboot without it. In this case however, you'll have to make sure : that you don't overwrite your ME/TXE firmware on your flash ROM. : : config ME_BIN_PATH : string "Path to management engine firmware" : default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/me.bin" : depends on HAVE_ME_BIN : : config CHECK_ME : bool "Verify the integrity of the supplied ME/TXE firmware" : default n : depends on HAVE_ME_BIN && (NORTHBRIDGE_INTEL_IRONLAKE || \ : NORTHBRIDGE_INTEL_SANDYBRIDGE || \ : NORTHBRIDGE_INTEL_HASWELL || \ : SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE || \ : SOC_INTEL_KABYLAKE || SOC_INTEL_BAYTRAIL || SOC_INTEL_BRASWELL) : help : Verify the integrity of the supplied Intel ME/TXE firmware before : proceeding with the build, in order to prevent an accidental loading : of a corrupted ME/TXE image. : : config ME_REGION_ALLOW_CPU_READ_ACCESS : bool "Allows HOST/CPU read access to ME region" : depends on HAVE_IFD_BIN : default y if SOC_INTEL_CSE_LITE_SKU : default n : help : The config ensures Host has read access to the ME region if it is locked : through LOCK_MANAGEMENT_ENGINE config. This config is enabled when the CSE : Lite SKU is integrated. : : config USE_ME_CLEANER : bool "Strip down the Intel ME/TXE firmware" : depends on HAVE_ME_BIN && (NORTHBRIDGE_INTEL_IRONLAKE || \ : NORTHBRIDGE_INTEL_SANDYBRIDGE || \ : NORTHBRIDGE_INTEL_HASWELL || \ : SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE || \ : SOC_INTEL_KABYLAKE || SOC_INTEL_BAYTRAIL || SOC_INTEL_BRASWELL) : help : Use me_cleaner to remove all the non-fundamental code from the Intel : ME/TXE firmware. : The resulting Intel ME/TXE firmware will have only the code : responsible for the very basic hardware initialization, leaving the : ME/TXE subsystem essentially in a disabled state. : : Don't flash a modified ME/TXE firmware and a new coreboot image at the : same time, test them in two different steps. : : WARNING: this tool isn't based on any official Intel documentation but : only on reverse engineering and trial & error. : : See the project's page : https://github.com/corna/me_cleaner : or the wiki : https://github.com/corna/me_cleaner/wiki/How-to-apply-me_cleaner : https://github.com/corna/me_cleaner/wiki/How-does-it-work%3F : https://github.com/corna/me_cleaner/wiki/me_cleaner-status : for more info about this tool : : If unsure, say N. : : comment "Please test the modified ME/TXE firmware and coreboot in two steps" : depends on USE_ME_CLEANER : : config ME_CLEANER_ARGS : string : depends on USE_ME_CLEANER : default "-S" : : config MAINBOARD_USES_IFD_GBE_REGION : def_bool n : : config HAVE_GBE_BIN : bool "Add gigabit ethernet configuration" : depends on HAVE_IFD_BIN && MAINBOARD_USES_IFD_GBE_REGION : help : The integrated gigabit ethernet controller needs a configuration : file. Select this if you are going to use the PCH integrated : controller and want to add that file. : : config GBE_BIN_PATH : string "Path to gigabit ethernet configuration" : depends on HAVE_GBE_BIN : default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/gbe.bin" : : config MAINBOARD_USES_IFD_EC_REGION : def_bool n : : config HAVE_EC_BIN : bool "Add EC firmware" : depends on HAVE_IFD_BIN && MAINBOARD_USES_IFD_EC_REGION : help : The embedded controller needs a firmware file. : : Select this if you are going to use the PCH integrated controller : and have the EC firmware. EC firmware will be added to final image : through ifdtool. : : config EC_BIN_PATH : string "Path to EC firmware" : depends on HAVE_EC_BIN : default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/ec.bin" : : choice : prompt "Protect flash regions" if HAVE_IFD_BIN : default UNLOCK_FLASH_REGIONS if HAVE_IFD_BIN : help : This option allows you to protect flash regions. : : config DO_NOT_TOUCH_DESCRIPTOR_REGION : bool "Use the preset values to protect the regions" : help : Read and write access permissions to different regions in the flash : can be controlled via dedicated bitfields in the flash descriptor. : These permissions can be modified with the Intel Flash Descriptor : Tool (ifdtool). If you don't want to change these permissions and : keep the ones provided in the initial descriptor, use this option. : : config LOCK_MANAGEMENT_ENGINE : bool "Lock ME/TXE section" : help : The Intel Firmware Descriptor supports preventing write and read : accesses from the host to the ME or TXE section. If the section : is locked, it can only be overwritten with an external SPI flash : programmer or HECI HMRFPO_ENABLE command needs to be sent to CSE : before writing to the ME Section. If CSE Lite SKU is integrated, : the Kconfig prevents only writing to the ME section. : : If unsure, select "Unlock flash regions". : : config UNLOCK_FLASH_REGIONS : bool "Unlock flash regions" : help : All regions are completely unprotected and can be overwritten using : a flash programming tool. : : endchoice > I'm not sure if the if-clause would make some symbols disappear. […] ``` Most items within an if/endif block are not evaluated, while others, such as the ‘source’ keyword, ignore the existence of the if/endif block completely. Symbols defined within an if/endif block are still created, although their default values are ignored - all values are set to ‘n’. ``` tl;dr the symbols are created, and all set to `n`. Using make menuconfig, it seems that `if/endif` or `depends on` can make prompts appear/disappear. -- To view, visit https://review.coreboot.org/c/coreboot/+/56107 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8736f32b4c695efbd68adf551e1376726c718b56 Gerrit-Change-Number: 56107 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 07 Jul 2021 22:07:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: drivers/intel/gma: Support IGD Opregion 2.1
by Tim Wawrzynczak (Code Review) 07 Jul '21

07 Jul '21

Attention is currently required from: Nico Huber, Krishna Prabhakaran, Furquan Shaikh, Maulik V Vaghela, Selma Bensaid, Subrata Banik, Meera Ravindranath, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52758 ) Change subject: drivers/intel/gma: Support IGD Opregion 2.1 ...................................................................... Patch Set 11: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52758 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95a9f3df185002a4e38faa910f867ace0b97ac2b Gerrit-Change-Number: 52758 Gerrit-PatchSet: 11 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Krishna Prabhakaran <krishna.prabhakaran(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Krishna Prabhakaran <krishna.prabhakaran(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 07 Jul 2021 21:58:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel: Fix microcode loading
by Paul Menzel (Code Review) 07 Jul '21

07 Jul '21

Attention is currently required from: Stefan Ott, Tim Wawrzynczak, Patrick Rudolph. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56153 ) Change subject: soc/intel: Fix microcode loading ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Indeed, this seems to fix that issue. […] Can you please add a Resolves: tag to the commit message? -- To view, visit https://review.coreboot.org/c/coreboot/+/56153 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62def8014fd3f3bbf607b4d58ddc4dca4c695622 Gerrit-Change-Number: 56153 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 07 Jul 2021 21:58:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Stefan Ott <coreboot(a)desire.ch> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel: Fix microcode loading
by Stefan Ott (Code Review) 07 Jul '21

07 Jul '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Stefan Ott has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56153 ) Change subject: soc/intel: Fix microcode loading ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: > Does this help with https://ticket.coreboot. […] Indeed, this seems to fix that issue. Thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/56153 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62def8014fd3f3bbf607b4d58ddc4dca4c695622 Gerrit-Change-Number: 56153 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 07 Jul 2021 21:55:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/alderlake: Avoid NULL pointer deference
by Tim Wawrzynczak (Code Review) 07 Jul '21

07 Jul '21

Attention is currently required from: John Zhao, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56123 ) Change subject: soc/intel/alderlake: Avoid NULL pointer deference ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56123 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I151157e7a9a90c43075f431933ac44f29fd25127 Gerrit-Change-Number: 56123 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <angel.pons(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 07 Jul 2021 21:46:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit July 2021