coreboot-gerrit July 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/alderlake: Switch to runtime generation of Intel Power Engine
by Cliff Huang (Code Review) 07 Jul '21

07 Jul '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56006 ) Change subject: soc/intel/alderlake: Switch to runtime generation of Intel Power Engine ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/56006 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I617bc3d1c3cf4ac6b6cbbd790dcf62e731024834 Gerrit-Change-Number: 56006 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 07 Jul 2021 20:14:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: Fix microcode loading
by Tim Wawrzynczak (Code Review) 07 Jul '21

07 Jul '21

Attention is currently required from: Stefan Ott, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56153 ) Change subject: soc/intel: Fix microcode loading ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Does this help with https://ticket.coreboot.org/issues/313 ? -- To view, visit https://review.coreboot.org/c/coreboot/+/56153 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62def8014fd3f3bbf607b4d58ddc4dca4c695622 Gerrit-Change-Number: 56153 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 07 Jul 2021 19:53:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/intel/microcode: Add support for extended signature table
by Tim Wawrzynczak (Code Review) 07 Jul '21

07 Jul '21

Attention is currently required from: Furquan Shaikh, Rizwan Qureshi. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54734 ) Change subject: src/intel/microcode: Add support for extended signature table ...................................................................... Patch Set 8: (2 comments) Patchset: PS8: > Seems like this change caused regressions: https://ticket.coreboot. […] Pending my approval on ticket.coreboot.org, does CB:56153 fix the issue? File src/cpu/intel/microcode/microcode.c: https://review.coreboot.org/c/coreboot/+/54734/comment/ebf02b0b_27d64916 PS8, Line 139: size_t ext_tbl_len = ucode->total_size - size; > ssize_t could be useful here to avoid overflows. […] CB:56153 is my suggestion -- To view, visit https://review.coreboot.org/c/coreboot/+/54734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1466caf4a4ba1f9a0214bdde19cce57dd65dacbd Gerrit-Change-Number: 54734 Gerrit-PatchSet: 8 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Comment-Date: Wed, 07 Jul 2021 19:52:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: Fix microcode loading
by Tim Wawrzynczak (Code Review) 07 Jul '21

07 Jul '21

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56153 ) Change subject: soc/intel: Fix microcode loading ...................................................................... soc/intel: Fix microcode loading Commit 1aa60a95bd8363d2 broke microcode loading for chipsets that have a microcode blob with a total_size field set to 0. This appears to be support for older chipsets, where the size was set to 0 and assumed to be 2048 bytes. The fix is to change the result of the subtraction to a signed type, and ensure the following comparison is done without promoting the signed type to an unsigned one. Change-Id: I62def8014fd3f3bbf607b4d58ddc4dca4c695622 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/cpu/intel/microcode/microcode.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/56153/1 diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 45996df..469bd25 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -136,9 +136,9 @@ /* header + ucode data blob size */ u32 size = ucode->data_size + sizeof(struct microcode); - size_t ext_tbl_len = ucode->total_size - size; + ssize_t ext_tbl_len = ucode->total_size - size; - if (ext_tbl_len < sizeof(struct ext_sig_table)) + if (ext_tbl_len < (ssize_t)sizeof(struct ext_sig_table)) return NULL; ext_tbl = (struct ext_sig_table *)((uintptr_t)ucode + size); -- To view, visit https://review.coreboot.org/c/coreboot/+/56153 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62def8014fd3f3bbf607b4d58ddc4dca4c695622 Gerrit-Change-Number: 56153 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya0: Update the FIVR configurations
by Tim Wawrzynczak (Code Review) 07 Jul '21

07 Jul '21

Attention is currently required from: V Sowmya, Kedar J. Karanje, Maulik V Vaghela, vagdevi.p(a)intel.com, Subrata Banik, Vinay Kumar. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55704 ) Change subject: mb/google/brya0: Update the FIVR configurations ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55704 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c4fdb38c5c56798935b2c6627a75c3f1ac9fbef Gerrit-Change-Number: 55704 Gerrit-PatchSet: 5 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: vagdevi.p(a)intel.com Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: vagdevi.p(a)intel.com Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Comment-Date: Wed, 07 Jul 2021 19:41:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/../car: Calculate SF Mask#1 based on MSR 0xc87
by Tim Wawrzynczak (Code Review) 07 Jul '21

07 Jul '21

Attention is currently required from: Furquan Shaikh, Subrata Banik, Nick Vaccaro, EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51374 ) Change subject: soc/intel/common/../car: Calculate SF Mask#1 based on MSR 0xc87 ...................................................................... Patch Set 8: (1 comment) File src/soc/intel/common/block/cpu/car/cache_as_ram.S: https://review.coreboot.org/c/coreboot/+/51374/comment/a02545f5_017653d0 PS8, Line 532: mov %al, %cl : mov $0x01, %eax : shl %cl, %eax : subl $0x01, %eax /* contains ((1 << SFWayCnt) - 1) */ : mov %bl, %cl : mov $0x01, %ebx : shl %cl, %ebx : subl $0x01, %ebx /* contains ((1 << data_ways) - 1) */ : sub %ebx, %eax /* contains SF mask */ > subl %ecx, %edi /* ecx == SFWayCnt - data_ways */ […] Oops, yes, I mixed up the order of registers in that line, you figured out what I meant 😉 Right, with this sequence, there are fewer instructions and `ebx` doesn't need to be saved/restored -- To view, visit https://review.coreboot.org/c/coreboot/+/51374 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd0b7e1a90cad4a4837adf6067fe8301dcd0a941 Gerrit-Change-Number: 51374 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Wed, 07 Jul 2021 19:23:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Switch to runtime generation of Intel Power Engine
by Tim Wawrzynczak (Code Review) 07 Jul '21

07 Jul '21

Attention is currently required from: Patrick Rudolph. Hello build bot (Jenkins), Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56007 to look at the new patch set (#3). Change subject: soc/intel/tigerlake: Switch to runtime generation of Intel Power Engine ...................................................................... soc/intel/tigerlake: Switch to runtime generation of Intel Power Engine The pep.asl file is being obsoleted by runtime generation, therefore switch tigerlake boards to this method. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I8e97c589273e934e89d69d8829680b9cac1ff9f5 --- M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/acpi/southbridge.asl M src/soc/intel/tigerlake/pmc.c 3 files changed, 6 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/56007/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/56007 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e97c589273e934e89d69d8829680b9cac1ff9f5 Gerrit-Change-Number: 56007 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Switch to runtime generation of Intel Power Engine
by Tim Wawrzynczak (Code Review) 07 Jul '21

07 Jul '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Hello build bot (Jenkins), Cliff Huang, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56006 to look at the new patch set (#2). Change subject: soc/intel/alderlake: Switch to runtime generation of Intel Power Engine ...................................................................... soc/intel/alderlake: Switch to runtime generation of Intel Power Engine The pep.asl file is being obsoleted by runtime generation, therefore switch alderlake boards to this method. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I617bc3d1c3cf4ac6b6cbbd790dcf62e731024834 --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/acpi/southbridge.asl M src/soc/intel/alderlake/pmc.c 3 files changed, 7 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/56006/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56006 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I617bc3d1c3cf4ac6b6cbbd790dcf62e731024834 Gerrit-Change-Number: 56006 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: lib/future: Implement Futures API
by Martin Roth (Code Review) 07 Jul '21

07 Jul '21

Attention is currently required from: Raul Rangel, Aaron Durbin, Furquan Shaikh, Marshall Dawson, Julius Werner, Eric Peers. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56048 ) Change subject: lib/future: Implement Futures API ...................................................................... Patch Set 4: (2 comments) File src/lib/Kconfig: https://review.coreboot.org/c/coreboot/+/56048/comment/f4fe6dbc_43383781 PS2, Line 103: bool > Add a prompt so it can be disabled for debug? After talking with Raul, it seems like disabling the feature at this level doesn't really make sense. If individual features make use of this, they might not have the ability to fall back to an alternative method. File src/lib/Makefile.inc: https://review.coreboot.org/c/coreboot/+/56048/comment/56da5d04_70ef61a0 PS2, Line 274: -y > Make dependent on the config option being enabled? After talking with Raul, it seems like disabling the feature at this level doesn't really make sense. If individual features make use of this, they might not have the ability to fall back to an alternative method. -- To view, visit https://review.coreboot.org/c/coreboot/+/56048 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I350aebcd07024a00b90495bf937f8bca5193d02f Gerrit-Change-Number: 56048 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Aaron Durbin <adurbin(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Comment-Date: Wed, 07 Jul 2021 19:06:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Enable I2S audio codecs on ADL-M RVP
by Anil Kumar K (Code Review) 07 Jul '21

07 Jul '21

Attention is currently required from: Sathyanarayana Nujella, Selma Bensaid, Tim Wawrzynczak. Hello Sathyanarayana Nujella, build bot (Jenkins), Selma Bensaid, Tim Wawrzynczak, Jairaj Arava, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52221 to look at the new patch set (#26). Change subject: mb/intel/adlrvp: Enable I2S audio codecs on ADL-M RVP ...................................................................... mb/intel/adlrvp: Enable I2S audio codecs on ADL-M RVP - Add configurability using FW_CONFIG field in CBI, to enable/disable I2S codec support for MAX98373 codecs - AUDIO=ADL_MAX98373_ALC5682I_I2S: enable max98373 codec using expansion board Bug=None Test=With CBI FW_CONFIG set to 0x100, check I2S audio output on expansion card Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com> Change-Id: If2649647e58c5f30e2b539d534adf2a4e68f4fda --- M src/mainboard/intel/adlrvp/Kconfig M src/mainboard/intel/adlrvp/Makefile.inc M src/mainboard/intel/adlrvp/devicetree_m.cb A src/mainboard/intel/adlrvp/fw_config.c M src/mainboard/intel/adlrvp/gpio_m.c 5 files changed, 86 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/52221/26 -- To view, visit https://review.coreboot.org/c/coreboot/+/52221 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2649647e58c5f30e2b539d534adf2a4e68f4fda Gerrit-Change-Number: 52221 Gerrit-PatchSet: 26 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Jairaj Arava <jairaj.arava(a)intel.com> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit July 2021