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Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56048 )
Change subject: lib/future: Implement Futures API
......................................................................
Patch Set 4:
(1 comment)
File src/lib/future.c:
https://review.coreboot.org/c/coreboot/+/56048/comment/513fac40_994a6bea
PS2, Line 68: state = futures[i]->poll(futures[i], false);
> So I was tempted to add a bunch of debug style information in the the futures object. […]
I'll leave it up to you - i think it might be useful to print something when a task actually gets executed, but not when it just checks to see if anything needs to happen. I'd be good with this happening later too, so we can actually decide whether or not it's needed.
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Change subject: commonlib/region: Add support for asynchronous readat
......................................................................
Patch Set 6:
(6 comments)
File src/commonlib/include/commonlib/region.h:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123584):
https://review.coreboot.org/c/coreboot/+/55856/comment/4858bcde_c280d6e5
PS6, Line 98: cb_err_t (*readat_async)(const struct region_device *,
function definition argument 'const struct region_device *' should also have an identifier name
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123584):
https://review.coreboot.org/c/coreboot/+/55856/comment/15480fb9_2b2f1ee7
PS6, Line 98: cb_err_t (*readat_async)(const struct region_device *,
function definition argument 'struct rdev_readat_async_context *' should also have an identifier name
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123584):
https://review.coreboot.org/c/coreboot/+/55856/comment/ec67aef3_6d80363c
PS6, Line 98: cb_err_t (*readat_async)(const struct region_device *,
function definition argument 'void *' should also have an identifier name
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123584):
https://review.coreboot.org/c/coreboot/+/55856/comment/e256d8c2_d1296569
PS6, Line 98: cb_err_t (*readat_async)(const struct region_device *,
function definition argument 'size_t' should also have an identifier name
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123584):
https://review.coreboot.org/c/coreboot/+/55856/comment/40380a99_af073cfc
PS6, Line 98: cb_err_t (*readat_async)(const struct region_device *,
function definition argument 'size_t' should also have an identifier name
File src/commonlib/region.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123584):
https://review.coreboot.org/c/coreboot/+/55856/comment/8d46befb_fdbd576d
PS6, Line 136: cb_err_t rdev_readat_async(const struct region_device *rd, struct rdev_readat_async_context *context,
line over 96 characters
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Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56087 )
Change subject: mb/google/volteer/var/voema: Remove stop delay time for ELAN TS
......................................................................
Patch Set 2: Code-Review+2
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I'd like you to reexamine a change. Please visit
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Change subject: soc/amd/{common,cezanne}: Implement HAVE_PAYLOAD_PRELOAD_CACHE
......................................................................
soc/amd/{common,cezanne}: Implement HAVE_PAYLOAD_PRELOAD_CACHE
This change allows preloading the payload.
BUG=b:179699789
TEST=Boot guybrush and see payload read/decompress drop by 23 ms.
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: I3ec78e628f24f2ba0c9fcf2a9e3bde64687eec44
---
M src/soc/amd/cezanne/Kconfig
M src/soc/amd/cezanne/fsp_s_params.c
M src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld
3 files changed, 13 insertions(+), 1 deletion(-)
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Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Felix Held,
I'd like you to reexamine a change. Please visit
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Change subject: WIP: soc/amd/common/block/lpc: Don't disable the HOG bit
......................................................................
WIP: soc/amd/common/block/lpc: Don't disable the HOG bit
This bit breaks SPI DMA.
BUG=b:179699789
TEST=Boot guybrush and see SPI DMA working
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: If015869657f36d3533f4ab9ebd1f54b0d4eb283b
---
M src/soc/amd/common/block/lpc/lpc.c
1 file changed, 1 insertion(+), 1 deletion(-)
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Change subject: lib/prog_loaders: Add payload_preload
......................................................................
lib/prog_loaders: Add payload_preload
This method will allow the SoC code to start loading the payload before
it is required.
BUG=b:177909625
TEST=Boot guybrush and see read/decompress drop by 23 ms.
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: Ifa8f30a0f4f931ece803c2e8e022e4d33d3fe581
---
M src/include/program_loading.h
M src/include/symbols.h
M src/lib/Kconfig
M src/lib/prog_loaders.c
4 files changed, 63 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/56051/5
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Change subject: lib/hardwaremain: Call poll_futures
......................................................................
lib/hardwaremain: Call poll_futures
This CL makes the ramstage state machine poll the futures after each
callback and during stage transitions. This will keep the futures
progressing throughout the boot process. This is a no-op for platforms
that don't set FUTURES_EXECUTOR.
BUG=b:177909625
TEST=Boot guybrush and see payload read/decompress drop by 23 ms.
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: I15e17ecb1094a4bfb7bf5cabe8c847b9e697ebf2
---
M src/lib/hardwaremain.c
1 file changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/56050/5
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Change subject: cbfs: Introduce and implement cbfs_load_async
......................................................................
cbfs: Introduce and implement cbfs_load_async
This CL adds support for the Futures API to cbfs. This allows loading a
file from CBFS asynchronously. It currently only supports uncompressed
files. More APIs will be added as I start to load stages, oproms, etc
asynchronously.
BUG=b:179699789
TEST=Boot guybrush and see payload read/decompress drop by 23 ms.
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: Idf4cee8a7094a9470aff997e4b06e823cb4811c0
---
M src/include/cbfs.h
M src/lib/cbfs.c
2 files changed, 184 insertions(+), 0 deletions(-)
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Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Felix Held,
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Change subject: soc/amd/cezanne: Start loading APOB asynchronously while FSP-M executes
......................................................................
soc/amd/cezanne: Start loading APOB asynchronously while FSP-M executes
In the S3 resume case we will block in `soc_fill_apob_cache`
until the whole buffer has been read since the PSP has not placed
the APOB contents into RAM.
In the non-S3 case, the PSP has placed the APOB contents into RAM,
so `soc_fill_apob_cache` uses that for FSP-M. By reading the SPI
contents while FSP-M is executing, the data will be ready by the time
`soc_update_apob_cache` executes.
We currently get lucky that the APOB is only 64 KiB since the SPI DMA
controller can perform this transaction in one shot. In order to support
larger payloads, or multiple transactions while FSP-M executes, we will
need FSP-M to call `poll_futures` periodically.
BUG=b:179699789
TEST=Boot guybrush and verify APOB read timestamp has dropped from 10ms
to a few uS.
FMAP: area RW_MRC_CACHE found @ 0 (65536 bytes)
spi_dma_readat_async: dest: 0x020935c0, offset: 0x0, size: 65536
spi_dma_async_poll: current_transaction: 0x020a3620
start_spi_dma_transaction: dest: 0x020935c0, offset: 0x0, remaining: 65536
<FSP-M executes>
wait_for_promise: waiting for promise
spi_dma_async_poll: current_transaction: 0x020a3620
continue_spi_dma_transaction: dest: 0x020935c0, offset: 0x0, remaining: 65536
spi_dma_async_poll: transaction complete
spi_dma_async_poll: current_transaction: 0x00000000
wait_for_promise: took 12 us
APOB valid copy is already in flash
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: I4b5c1ef4cad571d1cbca33b1aff017a3cedc1be8
---
M src/soc/amd/cezanne/fsp_m_params.c
1 file changed, 14 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/55859/7
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I'd like you to reexamine a change. Please visit
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Change subject: soc/amd/common/apob: Add support for asynchronously reading APOB
......................................................................
soc/amd/common/apob: Add support for asynchronously reading APOB
This CL adds a method that can starts the processes of reading the APOB
from SPI. It does take more RAM in romstage since we no longer mmap the
buffer in the async happy path. This will allow us to reduce our boot
time by 10ms.
We don't register the future with the executor since it's not currently
getting called in romstage, and the transfer completes in a single
transaction.
BUG=b:179699789
TEST=With this and the FSP patch above I can see a 10 ms reduction in
boot time on guybrush.
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: I930d58b76eb4558bc4f48ed928c4d6538fefbde7
---
M src/soc/amd/common/block/apob/apob_cache.c
M src/soc/amd/common/block/include/amdblocks/apob_cache.h
2 files changed, 33 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/55858/7
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