coreboot-gerrit July 2021

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Change in coreboot[master]: mb/intel/adlrvp_m: Enable EC software sync
by Selma Bensaid (Code Review) 08 Jul '21

08 Jul '21

Attention is currently required from: Bora Guvendik, Thejaswani Putta. Selma Bensaid has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56154 ) Change subject: mb/intel/adlrvp_m: Enable EC software sync ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/56154 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a13094e5da2f672a6789fe86528de44e909045e Gerrit-Change-Number: 56154 Gerrit-PatchSet: 1 Gerrit-Owner: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Comment-Date: Thu, 08 Jul 2021 01:15:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp_m: Enable EC software sync
by Thejaswani Putta (Code Review) 08 Jul '21

08 Jul '21

Thejaswani Putta has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56154 ) Change subject: mb/intel/adlrvp_m: Enable EC software sync ...................................................................... mb/intel/adlrvp_m: Enable EC software sync This patch enables CONFIG_VBOOT_EARLY_EC_SYNC. EC software sync will be performed in romstage. BUG=None BRANCH=None TEST=Verify EC software sync works on adlrvp_m Signed-off-by: Thejaswani Putta <thejaswani.putta(a)intel.com> Change-Id: I3a13094e5da2f672a6789fe86528de44e909045e --- M src/mainboard/intel/adlrvp/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/56154/1 diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig index 954c02e..8ed37ab 100644 --- a/src/mainboard/intel/adlrvp/Kconfig +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -27,7 +27,6 @@ select GBB_FLAG_FORCE_MANUAL_RECOVERY select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC select HAS_RECOVERY_MRC_CACHE - select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC config MAINBOARD_DIR string @@ -96,6 +95,7 @@ select VBOOT_LID_SWITCH select VBOOT_MOCK_SECDATA select EC_GOOGLE_CHROMEEC_SWITCHES if ADL_CHROME_EC + select VBOOT_EARLY_EC_SYNC if BOARD_INTEL_ADLRVP_M_EXT_EC config UART_FOR_CONSOLE int -- To view, visit https://review.coreboot.org/c/coreboot/+/56154 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a13094e5da2f672a6789fe86528de44e909045e Gerrit-Change-Number: 56154 Gerrit-PatchSet: 1 Gerrit-Owner: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel: Fix microcode loading
by Furquan Shaikh (Code Review) 08 Jul '21

08 Jul '21

Attention is currently required from: Stefan Ott, Tim Wawrzynczak, Paul Menzel, Patrick Rudolph. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56153 ) Change subject: soc/intel: Fix microcode loading ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56153 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62def8014fd3f3bbf607b4d58ddc4dca4c695622 Gerrit-Change-Number: 56153 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 08 Jul 2021 00:27:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [TESTONLY]do we use cbfs-relative base addresses as input??
by Julius Werner (Code Review) 08 Jul '21

08 Jul '21

Attention is currently required from: Arthur Heymans. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56044 ) Change subject: [TESTONLY]do we use cbfs-relative base addresses as input?? ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: I mean, if you remove this there'd be no more way at all to define a specific base for a file on non-x86 images, right? While I'm not aware of any board specifically using that right now it's probably not something we should make entirely impossible. -- To view, visit https://review.coreboot.org/c/coreboot/+/56044 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87349e98d6aeac5d3f79c8a067982cd136a0b863 Gerrit-Change-Number: 56044 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 08 Jul 2021 00:22:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: IMOK: Add IMOK method support for DPTF
by Tim Wawrzynczak (Code Review) 08 Jul '21

08 Jul '21

Attention is currently required from: Furquan Shaikh, Sumeet R Pawnikar, Patrick Rudolph, Aaron Durbin, Karthik Ramasubramanian. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54688 ) Change subject: IMOK: Add IMOK method support for DPTF ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54688 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8edfa3bcaa6bde0b9690fcace000cd582dcc81d2 Gerrit-Change-Number: 54688 Gerrit-PatchSet: 3 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 07 Jul 2021 23:05:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Add two sensors for DPTF functionality
by Tim Wawrzynczak (Code Review) 08 Jul '21

08 Jul '21

Attention is currently required from: Furquan Shaikh, Sumeet R Pawnikar, Aaron Durbin, Karthik Ramasubramanian. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54724 ) Change subject: mb/google/brya: Add two sensors for DPTF functionality ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Will this break any DPTF functionality on early boards that do not have all of the TSRs? -- To view, visit https://review.coreboot.org/c/coreboot/+/54724 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc9bd6040c9bb316ec7e314f5e9c937c75cfc95a Gerrit-Change-Number: 54724 Gerrit-PatchSet: 2 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 07 Jul 2021 23:02:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cannonlake mainboards: Set PMC as hidden in devicetree
by Tim Wawrzynczak (Code Review) 08 Jul '21

08 Jul '21

Attention is currently required from: Furquan Shaikh, Matt DeVillier, Jeremy Soller, Angel Pons, Karthik Ramasubramanian. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56008 ) Change subject: cannonlake mainboards: Set PMC as hidden in devicetree ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/56008/comment/ac289956_3daab1b1 PS2, Line 14: > Planning to verify this on google/dratini soon. Updated commit message -- To view, visit https://review.coreboot.org/c/coreboot/+/56008 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4a20ce9075ce7653388a5d3e281fe774bf89355 Gerrit-Change-Number: 56008 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 07 Jul 2021 23:00:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: cannonlake mainboards: Set PMC as hidden in devicetree
by Tim Wawrzynczak (Code Review) 08 Jul '21

08 Jul '21

Attention is currently required from: Furquan Shaikh, Matt DeVillier, Jeremy Soller, Angel Pons, Karthik Ramasubramanian. Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Matt DeVillier, Jeremy Soller, Angel Pons, Michael Niewöhner, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56008 to look at the new patch set (#3). Change subject: cannonlake mainboards: Set PMC as hidden in devicetree ...................................................................... cannonlake mainboards: Set PMC as hidden in devicetree FSP-S hides the PMC from the PCI bus when it runs, but there are still initialization steps coreboot programs for the PMC. Therefore, change all of the cannonlake mainboards to set the PMC as hidden in the devicetree, which means the device will be skipped during enumeration, but device callbacks are still issued as if the device were enabled. TEST=Ran full patch train on google/dratini, disassembled SSDT and the PEPD device matches what is in pep.asl. Also verified via dmesg that the INT33A1 device is still initialized by the kernel. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Ib4a20ce9075ce7653388a5d3e281fe774bf89355 --- M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb M src/mainboard/purism/librem_cnl/variants/librem_14/devicetree.cb M src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb M src/mainboard/system76/gaze15/devicetree.cb M src/mainboard/system76/lemp9/devicetree.cb M src/mainboard/system76/oryp5/devicetree.cb M src/mainboard/system76/oryp6/devicetree.cb M src/mainboard/system76/whl-u/devicetree.cb 12 files changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/56008/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/56008 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4a20ce9075ce7653388a5d3e281fe774bf89355 Gerrit-Change-Number: 56008 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/block/acpi: Move pep.asl to acpigen
by Tim Wawrzynczak (Code Review) 08 Jul '21

08 Jul '21

Attention is currently required from: Cliff Huang, Furquan Shaikh, Angel Pons, Michael Niewöhner, Patrick Rudolph, Karthik Ramasubramanian. Hello build bot (Jenkins), Cliff Huang, Furquan Shaikh, Angel Pons, Michael Niewöhner, Angel Pons, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56004 to look at the new patch set (#3). Change subject: soc/intel/common/block/acpi: Move pep.asl to acpigen ...................................................................... soc/intel/common/block/acpi: Move pep.asl to acpigen There is a use-case for generating the AML bytecode at runtime for the Intel Power Engine device, which comes in a followup patch. BUG=b:185437326 TEST=verified on google/brya and google/dratini by dumping SSDT and verifying the PEPD device matches what was previously in the DSDT: Scope (\_SB.PCI0) { Device (PEPD) { Name (_HID, "INT33A1") Name (_CID, EisaId ("PNP0D80") Method (_DSM, 4, Serialized) { ToBuffer (Arg0, Local0) If ((Local0 == ToUUID ("c4eb40a0-6cd2-11e2-bcfd-0800200c9a66"))) { ToInteger (Arg2, Local1) If ((Local1 == Zero)) { Return (Buffer (One) { 0x63 }) } If ((Local1 == One)) { Return (Package (0x01) { Package (0x03) { \NULL, Zero, Package (0x02) { Zero, Package (0x02) { 0xFF, Zero } } } }) } If ((Local1 == 0x02)){} If ((Local1 == 0x03)){} If ((Local1 == 0x04)){} If ((Local1 == 0x05)) { If (CondRefOf (\_SB.PCI0.LPCB.EC0.S0IX)) { \_SB.PCI0.LPCB.EC0.S0IX (One) } If (CondRefOf (\_SB.MS0X)) { \_SB.MS0X (One) } If (CondRefOf (\_SB.PCI0.EGPM)) { \_SB.PCI0.EGPM () } } If ((Local1 == 0x06)) { If (CondRefOf (\_SB.PCI0.LPCB.EC0.S0IX)) { \_SB.PCI0.LPCB.EC0.S0IX (Zero) } If (CondRefOf (\_SB.MS0X)) { \_SB.MS0X (Zero) } If (CondRefOf (\_SB.PCI0.RGPM)) { \_SB.PCI0.RGPM () } } Return (Buffer (One) { 0x00 }) } Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Ie83722e0ed5792e338fc5c39a57eef43b7464e3b --- M src/soc/intel/common/block/acpi/Kconfig M src/soc/intel/common/block/acpi/Makefile.inc A src/soc/intel/common/block/acpi/pep.c M src/soc/intel/common/block/include/intelblocks/acpi.h 4 files changed, 154 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/56004/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/56004 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie83722e0ed5792e338fc5c39a57eef43b7464e3b Gerrit-Change-Number: 56004 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: sb/intel/common: Hide IFD options if !HAVE_IFD_BIN
by Angel Pons (Code Review) 08 Jul '21

08 Jul '21

Attention is currently required from: Nico Huber, Tim Wawrzynczak, Arthur Heymans, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56107 ) Change subject: sb/intel/common: Hide IFD options if !HAVE_IFD_BIN ...................................................................... Patch Set 1: (1 comment) File src/southbridge/intel/common/firmware/Kconfig: https://review.coreboot.org/c/coreboot/+/56107/comment/1bcdcdbe_e48f8a5f PS1, Line 27: config HAVE_ME_BIN : bool "Add Intel ME/TXE firmware" : depends on HAVE_IFD_BIN : help : The Intel processor in the selected system requires a special firmware : for an integrated controller. This might be called the Management : Engine (ME), the Trusted Execution Engine (TXE) or something else : depending on the chip. This firmware might or might not be available : in coreboot's 3rdparty/blobs repository. If it is not and if you don't : have access to the firmware from elsewhere, you can still build : coreboot without it. In this case however, you'll have to make sure : that you don't overwrite your ME/TXE firmware on your flash ROM. : : config ME_BIN_PATH : string "Path to management engine firmware" : default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/me.bin" : depends on HAVE_ME_BIN : : config CHECK_ME : bool "Verify the integrity of the supplied ME/TXE firmware" : default n : depends on HAVE_ME_BIN && (NORTHBRIDGE_INTEL_IRONLAKE || \ : NORTHBRIDGE_INTEL_SANDYBRIDGE || \ : NORTHBRIDGE_INTEL_HASWELL || \ : SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE || \ : SOC_INTEL_KABYLAKE || SOC_INTEL_BAYTRAIL || SOC_INTEL_BRASWELL) : help : Verify the integrity of the supplied Intel ME/TXE firmware before : proceeding with the build, in order to prevent an accidental loading : of a corrupted ME/TXE image. : : config ME_REGION_ALLOW_CPU_READ_ACCESS : bool "Allows HOST/CPU read access to ME region" : depends on HAVE_IFD_BIN : default y if SOC_INTEL_CSE_LITE_SKU : default n : help : The config ensures Host has read access to the ME region if it is locked : through LOCK_MANAGEMENT_ENGINE config. This config is enabled when the CSE : Lite SKU is integrated. : : config USE_ME_CLEANER : bool "Strip down the Intel ME/TXE firmware" : depends on HAVE_ME_BIN && (NORTHBRIDGE_INTEL_IRONLAKE || \ : NORTHBRIDGE_INTEL_SANDYBRIDGE || \ : NORTHBRIDGE_INTEL_HASWELL || \ : SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE || \ : SOC_INTEL_KABYLAKE || SOC_INTEL_BAYTRAIL || SOC_INTEL_BRASWELL) : help : Use me_cleaner to remove all the non-fundamental code from the Intel : ME/TXE firmware. : The resulting Intel ME/TXE firmware will have only the code : responsible for the very basic hardware initialization, leaving the : ME/TXE subsystem essentially in a disabled state. : : Don't flash a modified ME/TXE firmware and a new coreboot image at the : same time, test them in two different steps. : : WARNING: this tool isn't based on any official Intel documentation but : only on reverse engineering and trial & error. : : See the project's page : https://github.com/corna/me_cleaner : or the wiki : https://github.com/corna/me_cleaner/wiki/How-to-apply-me_cleaner : https://github.com/corna/me_cleaner/wiki/How-does-it-work%3F : https://github.com/corna/me_cleaner/wiki/me_cleaner-status : for more info about this tool : : If unsure, say N. : : comment "Please test the modified ME/TXE firmware and coreboot in two steps" : depends on USE_ME_CLEANER : : config ME_CLEANER_ARGS : string : depends on USE_ME_CLEANER : default "-S" : : config MAINBOARD_USES_IFD_GBE_REGION : def_bool n : : config HAVE_GBE_BIN : bool "Add gigabit ethernet configuration" : depends on HAVE_IFD_BIN && MAINBOARD_USES_IFD_GBE_REGION : help : The integrated gigabit ethernet controller needs a configuration : file. Select this if you are going to use the PCH integrated : controller and want to add that file. : : config GBE_BIN_PATH : string "Path to gigabit ethernet configuration" : depends on HAVE_GBE_BIN : default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/gbe.bin" : : config MAINBOARD_USES_IFD_EC_REGION : def_bool n : : config HAVE_EC_BIN : bool "Add EC firmware" : depends on HAVE_IFD_BIN && MAINBOARD_USES_IFD_EC_REGION : help : The embedded controller needs a firmware file. : : Select this if you are going to use the PCH integrated controller : and have the EC firmware. EC firmware will be added to final image : through ifdtool. : : config EC_BIN_PATH : string "Path to EC firmware" : depends on HAVE_EC_BIN : default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/ec.bin" : : choice : prompt "Protect flash regions" if HAVE_IFD_BIN : default UNLOCK_FLASH_REGIONS if HAVE_IFD_BIN : help : This option allows you to protect flash regions. : : config DO_NOT_TOUCH_DESCRIPTOR_REGION : bool "Use the preset values to protect the regions" : help : Read and write access permissions to different regions in the flash : can be controlled via dedicated bitfields in the flash descriptor. : These permissions can be modified with the Intel Flash Descriptor : Tool (ifdtool). If you don't want to change these permissions and : keep the ones provided in the initial descriptor, use this option. : : config LOCK_MANAGEMENT_ENGINE : bool "Lock ME/TXE section" : help : The Intel Firmware Descriptor supports preventing write and read : accesses from the host to the ME or TXE section. If the section : is locked, it can only be overwritten with an external SPI flash : programmer or HECI HMRFPO_ENABLE command needs to be sent to CSE : before writing to the ME Section. If CSE Lite SKU is integrated, : the Kconfig prevents only writing to the ME section. : : If unsure, select "Unlock flash regions". : : config UNLOCK_FLASH_REGIONS : bool "Unlock flash regions" : help : All regions are completely unprotected and can be overwritten using : a flash programming tool. : : endchoice > ``` […] Right, so it would work because CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is only used in the choice block -- To view, visit https://review.coreboot.org/c/coreboot/+/56107 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8736f32b4c695efbd68adf551e1376726c718b56 Gerrit-Change-Number: 56107 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 07 Jul 2021 22:57:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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coreboot-gerrit July 2021