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Change subject: drivers/intel/gma: Define structure for Opregion version
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Patch Set 4:
(1 comment)
File src/drivers/intel/gma/opregion.c:
https://review.coreboot.org/c/coreboot/+/56168/comment/aca615d6_d7b6768e
PS3, Line 357: opregion->header.version = IGD_OPREGION_VERSION << 24;
> This is dropped without anything setting `over` fields.
Done that in the next CL here as I had to update the function of setting version -
https://review.coreboot.org/c/coreboot/+/52758
Do you recommend moving it to this CL?
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Change subject: mb/adlrvp: Fix DDR5 Boot issue
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Patch Set 19:
(1 comment)
File src/soc/intel/alderlake/meminit.c:
https://review.coreboot.org/c/coreboot/+/50996/comment/5637d22a_39009b77
PS19, Line 260: smbus_address_valid = true;
> DDR5 can be either memory-down or DIMMs. […]
+2 on splitting the code nicely between mainboard and SoC, i was not very happy to hardcode SMBUS address in SoC code earlier.
Just one question for Furquan on board design side, so you see DDR5 memory's are soldered down on always socketed on ref design? if both possible then ".topo" make sense to me.
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