coreboot-gerrit July 2021

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Change in coreboot[master]: vc/mediatek/mt8195: Enable DRAM Vcore DVFS settings
by Rex-BC Chen (Code Review) 09 Jul '21

09 Jul '21

Attention is currently required from: Rex-BC Chen, Paul Menzel, Yu-Ping Wu. Hello Hung-Te Lin, build bot (Jenkins), Ryan Chuang, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56106 to look at the new patch set (#9). Change subject: vc/mediatek/mt8195: Enable DRAM Vcore DVFS settings ...................................................................... vc/mediatek/mt8195: Enable DRAM Vcore DVFS settings Add the implementation for vcore voltage control. Also remove the reporting of vio18 because it is fixed during DRAM init, and we won't provide drivers for reading or writing it. Signed-off-by: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com> Change-Id: I39342aea902a87cdc2c5b862e5d1a889fcc822c5 --- M src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c M src/vendorcode/mediatek/mt8195/dramc/dramc_top.c 2 files changed, 6 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/56106/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/56106 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39342aea902a87cdc2c5b862e5d1a889fcc822c5 Gerrit-Change-Number: 56106 Gerrit-PatchSet: 9 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: vc/mediatek/mt8195: Enable DRAM Vcore DVFS settings
by Hung-Te Lin (Code Review) 09 Jul '21

09 Jul '21

Attention is currently required from: Rex-BC Chen, Paul Menzel, Yu-Ping Wu. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56106 ) Change subject: vc/mediatek/mt8195: Enable DRAM Vcore DVFS settings ...................................................................... Patch Set 8: (1 comment) File src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c: https://review.coreboot.org/c/coreboot/+/56106/comment/455849b2_9b207bbc PS7, Line 275: print("Vio18 = %d\n", dramc_get_vio18_voltage()); > vio18 is fixed at 1.8 volts, it will not be adjusted during dram init, […] So it'll simply show 0? given it's only for debugging I think it's probably fine? If you really want to remove it, please add a comment in the description for example Add the implementation for vcore voltage control. Also remove the reporting of vio18 because it is fixed during DRAM init, and we won't provide drivers for reading or writing it. -- To view, visit https://review.coreboot.org/c/coreboot/+/56106 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39342aea902a87cdc2c5b862e5d1a889fcc822c5 Gerrit-Change-Number: 56106 Gerrit-PatchSet: 8 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 09 Jul 2021 02:29:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: vc/mediatek/mt8195: Enable DRAM Vcore DVFS settings
by Rex-BC Chen (Code Review) 09 Jul '21

09 Jul '21

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56106 ) Change subject: vc/mediatek/mt8195: Enable DRAM Vcore DVFS settings ...................................................................... Patch Set 8: (3 comments) File src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c: https://review.coreboot.org/c/coreboot/+/56106/comment/0ed9541d_b5dd0abf PS5, Line 275: print("Vio18 = %d\n", dramc_get_vio18_voltage()); > Why is this removed? vio18 is fixed at 1.8 volts, it will not be adjusted during dram init, and pmic does not provide a driver for reading and writing vio18, so remove this line. File src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c: https://review.coreboot.org/c/coreboot/+/56106/comment/12361572_0e9b51fe PS7, Line 275: print("Vio18 = %d\n", dramc_get_vio18_voltage()); > please explain why you have to remove this in this patch. vio18 is fixed at 1.8 volts, it will not be adjusted during dram init, and pmic does not provide a driver for reading and writing vio18, so remove this line. File src/vendorcode/mediatek/mt8195/dramc/dramc_top.c: https://review.coreboot.org/c/coreboot/+/56106/comment/88594f93_f057b237 PS7, Line 356: d > %u (vcore is unsigned) Done -- To view, visit https://review.coreboot.org/c/coreboot/+/56106 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39342aea902a87cdc2c5b862e5d1a889fcc822c5 Gerrit-Change-Number: 56106 Gerrit-PatchSet: 8 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 09 Jul 2021 02:21:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: vc/mediatek/mt8195: Enable DRAM Vcore DVFS settings
by Rex-BC Chen (Code Review) 09 Jul '21

09 Jul '21

Attention is currently required from: Rex-BC Chen, Paul Menzel, Yu-Ping Wu. Hello Hung-Te Lin, build bot (Jenkins), Ryan Chuang, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56106 to look at the new patch set (#8). Change subject: vc/mediatek/mt8195: Enable DRAM Vcore DVFS settings ...................................................................... vc/mediatek/mt8195: Enable DRAM Vcore DVFS settings Signed-off-by: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com> Change-Id: I39342aea902a87cdc2c5b862e5d1a889fcc822c5 --- M src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c M src/vendorcode/mediatek/mt8195/dramc/dramc_top.c 2 files changed, 6 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/56106/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/56106 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39342aea902a87cdc2c5b862e5d1a889fcc822c5 Gerrit-Change-Number: 56106 Gerrit-PatchSet: 8 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: grunt/treeya: add Realtek ALC5682 codec support
by Daniel Kurtz (Code Review) 09 Jul '21

09 Jul '21

Attention is currently required from: Daniel Kurtz, Martin Roth, Kevin Chang, Paul Menzel. Daniel Kurtz has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56100 ) Change subject: grunt/treeya: add Realtek ALC5682 codec support ...................................................................... Patch Set 4: Code-Review-1 (8 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/56100/comment/698f7f24_cad45217 PS4, Line 10: A very brief description of *why* this patch is needed and what hardware models it effects would be useful. https://review.coreboot.org/c/coreboot/+/56100/comment/972580ac_54450765 PS4, Line 13: TEST=emerge-grunt coreboot I hope you did more than build test. Please explain what other tests were used to ensure this patch does as intended and no more or less. File src/mainboard/google/kahlee/variants/treeya/audio.c: https://review.coreboot.org/c/coreboot/+/56100/comment/ea58bb3e_4e8de77a PS4, Line 15: sku = google_chromeec_get_sku_id(); nit: I'd move this sku = ... down to where it is actually used (just before line 44). In fact, the variable isn't needed at all, just inline the function call: switch (google_chromeec_get_sku_id()) { https://review.coreboot.org/c/coreboot/+/56100/comment/7b48b608_4f792634 PS4, Line 21: if (mmio_dev == NULL) : break; > I think Paul is saying that this check should be your return. Martin, is "== NULL" a common thing in coreboot? In kernel land, this pattern would more often be "if (!mmio_dev)". (and yes, to simplify the code, the printk & return from lines 25-28 should just be moved here) https://review.coreboot.org/c/coreboot/+/56100/comment/56cbdc0a_fc46af6e PS4, Line 29: nit: I'd add a brief comment here describing what this next loop is doing. https://review.coreboot.org/c/coreboot/+/56100/comment/fba345f3_748db6b9 PS4, Line 45: default: : /* da7219 only */ : if (da7219_dev) : da7219_dev->enabled = 1; : if (alc_dev) : alc_dev->enabled = 0; : break; : nit: It seems a bit awkward to have default first in a switch statement. File src/mainboard/google/kahlee/variants/treeya/devicetree.cb: https://review.coreboot.org/c/coreboot/+/56100/comment/81e3a3c8_8bb97bf4 PS4, Line 126: 1a here you are explicitly configuring the Audio codec i2c address 0x1a (which is the same as da7219 above). Can you use this as the source of truth at runtime while matching, instead of hard-coding this same value as a constant in another file? File src/soc/amd/stoneyridge/include/soc/iomap.h: https://review.coreboot.org/c/coreboot/+/56100/comment/e3ff1b7b_a516224f PS4, Line 17: #define I2C_DEVICE_PATH 0x1a No, this board-specific audio component specific I2C address does not belong here in general SoC constants land. Also I'm not sure what you mean here by "PATH". -- To view, visit https://review.coreboot.org/c/coreboot/+/56100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49c673fd944b2c2a79c4283eee941a16596ba7fa Gerrit-Change-Number: 56100 Gerrit-PatchSet: 4 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)chromium.org> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alec Wang <alec.wang(a)lcfc.corp-partner.google.com> Gerrit-CC: Allen Cheng <allen.cheng(a)lcfc.corp-partner.google.com> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Daniel Kurtz <djkurtz(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 09 Jul 2021 01:58:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: vc/mediatek/mt8195: Enable DRAM Vcore DVFS settings
by Hung-Te Lin (Code Review) 09 Jul '21

09 Jul '21

Attention is currently required from: Rex-BC Chen, Paul Menzel, Yu-Ping Wu. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56106 ) Change subject: vc/mediatek/mt8195: Enable DRAM Vcore DVFS settings ...................................................................... Patch Set 7: (2 comments) File src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c: https://review.coreboot.org/c/coreboot/+/56106/comment/bbf21555_2ffa83a4 PS7, Line 275: print("Vio18 = %d\n", dramc_get_vio18_voltage()); please explain why you have to remove this in this patch. File src/vendorcode/mediatek/mt8195/dramc/dramc_top.c: https://review.coreboot.org/c/coreboot/+/56106/comment/c2d81b56_bf8e1493 PS7, Line 356: d %u (vcore is unsigned) -- To view, visit https://review.coreboot.org/c/coreboot/+/56106 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39342aea902a87cdc2c5b862e5d1a889fcc822c5 Gerrit-Change-Number: 56106 Gerrit-PatchSet: 7 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 09 Jul 2021 01:54:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: vc/mediatek/mt8195: add FOR_COREBOOT define
by Hung-Te Lin (Code Review) 09 Jul '21

09 Jul '21

Attention is currently required from: Rex-BC Chen, Yu-Ping Wu. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56158 ) Change subject: vc/mediatek/mt8195: add FOR_COREBOOT define ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56158 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7a6e24f41c1fda167b5d6bb2d8a2c5c79dda8de Gerrit-Change-Number: 56158 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 09 Jul 2021 01:52:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variants/primus, gimble: Update the FIVR configurations
by Casper Chang (Code Review) 09 Jul '21

09 Jul '21

Attention is currently required from: Malik Hsu, Tim Wawrzynczak, Mark Hsieh, Anfernee Chen, Casper Chang. Hello build bot (Jenkins), Malik Hsu, Tim Wawrzynczak, Mark Hsieh, Anfernee Chen, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56165 to look at the new patch set (#2). Change subject: mb/google/brya/variants/primus, gimble: Update the FIVR configurations ...................................................................... mb/google/brya/variants/primus, gimble: Update the FIVR configurations This patch sets the disable the external voltage rails since brya board doesn't have V1p05 and Vnn bypass rails implemented. Reference CB:55704 BUG=b:191897776, b:191213263 Signed-off-by: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Change-Id: I5c6b97e0b003560e1e22c96c5c3a1328fe876f47 --- M src/mainboard/google/brya/variants/gimble/overridetree.cb M src/mainboard/google/brya/variants/primus/overridetree.cb 2 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/56165/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56165 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c6b97e0b003560e1e22c96c5c3a1328fe876f47 Gerrit-Change-Number: 56165 Gerrit-PatchSet: 2 Gerrit-Owner: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Attention: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Attention: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-Attention: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/variants/primus, gimble: Update the FIVR configurations
by build bot (Jenkins) (Code Review) 09 Jul '21

09 Jul '21

Attention is currently required from: Tim Wawrzynczak. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56165 ) Change subject: mb/google/brya/variants/primus, gimble: Update the FIVR configurations ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/brya/variants/gimble/overridetree.cb: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123662): https://review.coreboot.org/c/coreboot/+/56165/comment/48abadc5_74e1d2f1 PS1, Line 29: trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/56165 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c6b97e0b003560e1e22c96c5c3a1328fe876f47 Gerrit-Change-Number: 56165 Gerrit-PatchSet: 1 Gerrit-Owner: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 09 Jul 2021 01:14:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variants/primus, gimble: Update the FIVR configurations
by Casper Chang (Code Review) 09 Jul '21

09 Jul '21

Casper Chang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56165 ) Change subject: mb/google/brya/variants/primus, gimble: Update the FIVR configurations ...................................................................... mb/google/brya/variants/primus, gimble: Update the FIVR configurations This patch sets the disable the external voltage rails since brya board doesn't have V1p05 and Vnn bypass rails implemented. Reference CB:55704 BUG=b:191897776, b:191213263 Signed-off-by: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Change-Id: I5c6b97e0b003560e1e22c96c5c3a1328fe876f47 --- M src/mainboard/google/brya/variants/gimble/overridetree.cb M src/mainboard/google/brya/variants/primus/overridetree.cb 2 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/56165/1 diff --git a/src/mainboard/google/brya/variants/gimble/overridetree.cb b/src/mainboard/google/brya/variants/gimble/overridetree.cb index 914a8bf..e5bab8f 100644 --- a/src/mainboard/google/brya/variants/gimble/overridetree.cb +++ b/src/mainboard/google/brya/variants/gimble/overridetree.cb @@ -20,6 +20,13 @@ end end chip soc/intel/alderlake + + # FIVR configurations for brya are disabled since the board doesn't have V1p05 and Vnn + # bypass rails implemented. + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + }" + register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Disable USB2_C2 register "usb2_ports[3]" = "USB2_PORT_EMPTY" # M.2 WWAN register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port diff --git a/src/mainboard/google/brya/variants/primus/overridetree.cb b/src/mainboard/google/brya/variants/primus/overridetree.cb index 36d015d..8ada763 100644 --- a/src/mainboard/google/brya/variants/primus/overridetree.cb +++ b/src/mainboard/google/brya/variants/primus/overridetree.cb @@ -23,6 +23,12 @@ chip soc/intel/alderlake + # FIVR configurations for brya are disabled since the board doesn't have V1p05 and Vnn + # bypass rails implemented. + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + }" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | -- To view, visit https://review.coreboot.org/c/coreboot/+/56165 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c6b97e0b003560e1e22c96c5c3a1328fe876f47 Gerrit-Change-Number: 56165 Gerrit-PatchSet: 1 Gerrit-Owner: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit July 2021