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Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56168
to look at the new patch set (#4).
Change subject: drivers/intel/gma: Define structure for Opregion version
......................................................................
drivers/intel/gma: Define structure for Opregion version
Align Opregion version fields to spec.
BUG=b:190019970
BRANCH=None
Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com>
Change-Id: I93a9f2df186002a4e38caa910f867bce0b97ac2b
---
M src/drivers/intel/gma/opregion.c
M src/drivers/intel/gma/opregion.h
2 files changed, 6 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/56168/4
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Change subject: drivers/intel/gma: Define structure for Opregion version
......................................................................
Patch Set 3:
(2 comments)
File src/drivers/intel/gma/opregion.h:
https://review.coreboot.org/c/coreboot/+/56168/comment/45f942fe_bd70bebf
PS3, Line 21:
One less tab is required.
File src/drivers/intel/gma/opregion.c:
https://review.coreboot.org/c/coreboot/+/56168/comment/f2c6c59c_87e5cdc3
PS3, Line 357: opregion->header.version = IGD_OPREGION_VERSION << 24;
This is dropped without anything setting `over` fields.
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Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50996 )
Change subject: mb/adlrvp: Fix DDR5 Boot issue
......................................................................
Patch Set 19:
(2 comments)
File src/soc/intel/alderlake/meminit.c:
https://review.coreboot.org/c/coreboot/+/50996/comment/1b3624c7_c229d848
PS19, Line 224: spd_addr_array
This is something that is very mainboard specific. Also, `mem_spd` (https://review.coreboot.org/plugins/gitiles/coreboot/+/4676279151659922da87…) already provides a member `addr_dimm` that can be used. Please see comment below.
https://review.coreboot.org/c/coreboot/+/50996/comment/f81999e4_305ce4b2
PS19, Line 260: smbus_address_valid = true;
DDR5 can be either memory-down or DIMMs. The current limitation is only for mainboards that are using DIMMs since SMBUS driver in coreboot is not yet updated to support DDR5 EEPROMs. Given that I think we should handle this as follows:
```
/*
* TODO: Drop this workaround once SMBus driver in coreboot is updated to
* support DDR5 EEPROM reading.
*/
if (spd_info->topo == MEM_TOPO_DIMM_MODULE) {
ddr5_fill_dimm_module_info(mem_cfg, mb_cfg, spd_info);
return;
}
```
and the above function can be:
```
#define DDR5_CH_DIMM_OFFSET(ch, dimm) ((ch) * CONFIG_DIMMS_PER_CHANNEL + (dimm))
static void ddr5_fill_dimm_module_info(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg, const struct mem_spd *spd_info)
{
for (size_t ch = 0; ch < soc_mem_cfg[MEM_TYPE_DDR5].num_phys_channels; ch++) {
for (size_t dimm = 0; dimm < CONFIG_DIMMS_PER_CHANNEL; dimm++) {
size_t mrc_ch = soc_mem_cfg[MEM_TYPE_DDR5].phys_to_mrc_map[ch];
mem_cfg->SpdAddressTable[DDR5_CH_DIMM_OFFSET(mrc_ch, dimm)] = info->smbus[ch].addr_dimm[dimm];
}
}
mem_init_dq_upds(mem_cfg, NULL, mb_cfg, true);
mem_init_dqs_upds(mem_cfg, NULL, mb_cfg, true);
}
```
In mainboard, you will have to configure ddr5_spd_info just like you currently do it for ddr4:
```
» const struct mem_spd ddr5_spd_info = {
» » .topo = MEM_TOPO_DIMM_MODULE,
» » .smbus = {
» » » [0] = {
» » » » .addr_dimm[0] = 0xa0,
» » » » .addr_dimm[1] = 0xa2,
» » » },
» » » [2] = {
» » » » .addr_dimm[0] = 0xa4,
» » » » .addr_dimm[1] = 0xa6,
» » » },
» » },
» };
```
Once SMBus support is added for DDR5, then only the workaround in SoC will have to be dropped. Mainboard code will remain unchanged.
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Attention is currently required from: Meera Ravindranath, Patrick Rudolph.
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56168
to look at the new patch set (#3).
Change subject: drivers/intel/gma: Define structure for Opregion version
......................................................................
drivers/intel/gma: Define structure for Opregion version
Align Opregion version fields to spec.
BUG=b:190019970
BRANCH=None
Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com>
Change-Id: I93a9f2df186002a4e38caa910f867bce0b97ac2b
---
M src/drivers/intel/gma/opregion.c
M src/drivers/intel/gma/opregion.h
2 files changed, 6 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/56168/3
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Hello Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56168
to look at the new patch set (#2).
Change subject: drivers/intel/gma: Define structure for Opregion version
......................................................................
drivers/intel/gma: Define structure for Opregion version
Align Opregion version fields to spec.
BUG=b:190019970
BRANCH=None
Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com>
Change-Id: I93a9f2df186002a4e38caa910f867bce0b97ac2b
---
M src/drivers/intel/gma/opregion.c
M src/drivers/intel/gma/opregion.h
2 files changed, 8 insertions(+), 23 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/56168/2
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Hello build bot (Jenkins), SRIDHAR SIRICILLA, Furquan Shaikh, Rizwan Qureshi, Tim Wawrzynczak, Sridhar Siricilla, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#56).
Change subject: soc/intel: Allow enable/disable ME via CMOS
......................................................................
soc/intel: Allow enable/disable ME via CMOS
Added .enable method that will set the CSME state.
State is based on me_state, with values of 0 and 1.
Method is very stable, reliable, and easy to change even
between different firmware platforms.
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
Change-Id: I374db3b7c0ded71cdc18f27970252fec7220cc20
---
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/include/intelblocks/cse.h
2 files changed, 127 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/52800/56
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