coreboot-gerrit July 2021

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Change in coreboot[master]: util/inteltool: Add basic support for Tiger Lake chips
by Michał Żygowski (Code Review) 09 Jul '21

09 Jul '21

Attention is currently required from: Stefan Reinauer. Hello build bot (Jenkins), Stefan Reinauer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56171 to look at the new patch set (#2). Change subject: util/inteltool: Add basic support for Tiger Lake chips ...................................................................... util/inteltool: Add basic support for Tiger Lake chips Add PCI IDs for Tiger Lake and Tiger Lake H devices and Tiger Point LP GPIO table. Tiger Point H GPIO table not yet implemented. TEST: dump GPIOs on i5-1135G7 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I6071a999be9e8a372997db0369218f297e579d08 --- M util/inteltool/gpio.c M util/inteltool/gpio_groups.c A util/inteltool/gpio_names/tigerlake_lp.h M util/inteltool/inteltool.c M util/inteltool/inteltool.h M util/inteltool/pcr.c 6 files changed, 493 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/56171/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56171 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6071a999be9e8a372997db0369218f297e579d08 Gerrit-Change-Number: 56171 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: supermicro/x11-lga1151-series: Remove SkipExtGfxScan = 1
by Nico Huber (Code Review) 09 Jul '21

09 Jul '21

Attention is currently required from: Jan Tatje, Michael Niewöhner. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56071 ) Change subject: supermicro/x11-lga1151-series: Remove SkipExtGfxScan = 1 ...................................................................... Patch Set 3: (1 comment) Patchset: PS2: > Exactly, there is no IGD. […] Ah, I guess the only difference it makes with coreboot is if IVD gets set. Everything else (wrt. PrimaryDisplay) can be handled without FSP. -- To view, visit https://review.coreboot.org/c/coreboot/+/56071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41249112c65927b61ca5f791f8eb8c3f3d204fce Gerrit-Change-Number: 56071 Gerrit-PatchSet: 3 Gerrit-Owner: Jan Tatje <jan(a)jnt.io> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jan Tatje <jan(a)jnt.io> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Fri, 09 Jul 2021 14:44:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Jan Tatje <jan(a)jnt.io> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Set max Pkg C-states to Auto
by Tim Wawrzynczak (Code Review) 09 Jul '21

09 Jul '21

Attention is currently required from: V Sowmya, Kedar J. Karanje, Maulik V Vaghela, vagdevi.p(a)intel.com, Subrata Banik, Vinay Kumar, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55706 ) Change subject: soc/intel/alderlake: Set max Pkg C-states to Auto ...................................................................... Patch Set 7: Code-Review+1 (1 comment) Patchset: PS7: Is there any effective difference between AUTO and C10 ? -- To view, visit https://review.coreboot.org/c/coreboot/+/55706 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab92eaadad3f17ed8dddc4f383d6eeaab8c9ea6e Gerrit-Change-Number: 55706 Gerrit-PatchSet: 7 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: vagdevi.p(a)intel.com Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: vagdevi.p(a)intel.com Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 09 Jul 2021 14:35:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: util/inteltool: Add basic support for Tiger Lake chips
by Michał Żygowski (Code Review) 09 Jul '21

09 Jul '21

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56171 ) Change subject: util/inteltool: Add basic support for Tiger Lake chips ...................................................................... util/inteltool: Add basic support for Tiger Lake chips Add PCI IDs for Tiger Lake and Tiger Lake H devices and Tiger Point LP GPIO table. Tiger Point H GPIO table not yet implemented. TEST: dump GPIOs on i5-1135G7 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I6071a999be9e8a372997db0369218f297e579d08 --- M util/inteltool/gpio.c M util/inteltool/gpio_groups.c A util/inteltool/gpio_names/tigerlake_lp.h M util/inteltool/inteltool.c M util/inteltool/inteltool.h M util/inteltool/pcr.c 6 files changed, 493 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/56171/1 diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index 22bad0e..d7653c3 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -1039,6 +1039,11 @@ case PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM: case PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_PREM: case PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_BASE: + case PCI_DEVICE_ID_INTEL_TIGERPOINT_U_SUPER: + case PCI_DEVICE_ID_INTEL_TIGERPOINT_U_PREM: + case PCI_DEVICE_ID_INTEL_TIGERPOINT_U_BASE: + case PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_SUPER: + case PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_PREM: case PCI_DEVICE_ID_INTEL_C621: case PCI_DEVICE_ID_INTEL_C622: case PCI_DEVICE_ID_INTEL_C624: diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index 0ff1c86..3226d63 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -17,6 +17,7 @@ #include "gpio_names/icelake.h" #include "gpio_names/lewisburg.h" #include "gpio_names/sunrise.h" +#include "gpio_names/tigerlake_lp.h" #define SBBAR_SIZE (16 * MiB) #define PCR_PORT_SIZE (64 * KiB) @@ -149,6 +150,14 @@ *community_count = ARRAY_SIZE(cannonlake_pch_lp_communities); *pad_stepping = 16; return cannonlake_pch_lp_communities; + case PCI_DEVICE_ID_INTEL_TIGERPOINT_U_SUPER: + case PCI_DEVICE_ID_INTEL_TIGERPOINT_U_PREM: + case PCI_DEVICE_ID_INTEL_TIGERPOINT_U_BASE: + case PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_SUPER: + case PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_PREM: + *community_count = ARRAY_SIZE(tigerlake_pch_lp_communities); + *pad_stepping = 16; + return tigerlake_pch_lp_communities; case PCI_DEVICE_ID_INTEL_H310: case PCI_DEVICE_ID_INTEL_H370: case PCI_DEVICE_ID_INTEL_Z390: diff --git a/util/inteltool/gpio_names/tigerlake_lp.h b/util/inteltool/gpio_names/tigerlake_lp.h new file mode 100644 index 0000000..6dc7216 --- /dev/null +++ b/util/inteltool/gpio_names/tigerlake_lp.h @@ -0,0 +1,397 @@ +#ifndef GPIO_NAMES_TIGERLAKE_LP +#define GPIO_NAMES_TIGERLAKE_LP + +#include "gpio_groups.h" + +const char *const tigerlake_pch_lp_group_a_names[] = { + "GPP_A0", "ESPI_IO0", "n/a", "n/a", "n/a", "n/a", + "GPP_A1", "ESPI_IO1", "n/a", "n/a", "n/a", "n/a", + "GPP_A2", "ESPI_IO2", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a", "n/a", + "GPP_A3", "ESPI_IO3", "SUSACK#", "n/a", "n/a", "n/a", + "GPP_A4", "ESPI_CS#", "n/a", "n/a", "n/a", "n/a", + "GPP_A5", "ESPI_CLK", "n/a", "n/a", "n/a", "n/a", + "GPP_A6", "ESPI_RESET#", "n/a", "n/a", "n/a", "n/a", + "GPP_A7", "I2S2_SCLK", "n/a", "n/a", "n/a", "DMIC_CLK_A0", + "GPP_A8", "I2S2_SFRM", "CNV_RF_RESET#", "n/a", "n/a", "DMIC_DATA0", + "GPP_A9", "I2S2_TXD", "MODEM_CLKREQ", "CRF_XTAL_CLKREQ", "n/a", "DMIC_CLK_A1", + "GPP_A10", "I2S2_RXD", "n/a", "n/a", "n/a", "DMIC_DATA1", + "GPP_A11", "PMC_I2C_SDA", "n/a", "I2S3_SCLK", "n/a", "n/a", + "GPP_A12", "SATAXPCIE1", "SATAGP1", "I2S3_SFRM", "n/a", "n/a", + "GPP_A13", "PMC_I2C_SCL", "n/a", "I2S3_TXD", "n/a", "DMIC_CLK_B0", + "GPP_A14", "USB_OC1#", "DDSP_HPD3", "I2S3_RXD", "DISP_MISC3", "DMIC_CLK_B1", + "GPP_A15", "USB_OC2#", "DDSP_HPD4", "I2S4_SCLK", "DISP_MISC4", "n/a", + "GPP_A16", "USB_OC3#", "n/a", "I2S4_SFRM", "n/a", "n/a", + "GPP_A17", "n/a", "DISP_MISCC", "I2S4_TXD", "n/a", "n/a", + "GPP_A18", "DDSP_HPDB", "DISP_MISCB", "I2S4_RXD", "n/a", "n/a", + "GPP_A19", "DDSP_HPD1", "DISP_MISC1", "I2S5_SCLK", "n/a", "n/a", + "GPP_A20", "DDSP_HPD2", "DISP_MISC2", "I2S5_SFRM", "n/a", "n/a", + "GPP_A21", "n/a", "DDPC_CTRLCLK", "I2S5_TXD", "n/a", "n/a", + "GPP_A22", "n/a", "DDPC_CTRLDATA", "I2S5_RXD", "n/a", "n/a", + "GPP_A23", "I2S1_SCLK", "n/a", "n/a", "n/a", "n/a", + "ESPI_CLK_LOOPBK", "ESPI_CLK_LOOPBK", "n/a", "n/a", "n/a", "n/a", +}; + +const struct gpio_group tigerlake_pch_lp_group_a = { + .display = "------- GPIO Group GPP_A -------", + .pad_count = ARRAY_SIZE(tigerlake_pch_lp_group_a_names) / 6, + .func_count = 6, + .pad_names = tigerlake_pch_lp_group_a_names, +}; + +const char *const tigerlake_pch_lp_group_b_names[] = { + "GPP_B0", "CORE_VID0", "n/a", "n/a", + "GPP_B1", "CORE_VID1", "n/a", "n/a", + "GPP_B2", "VRALERT#", "n/a", "n/a", + "GPP_B3", "CPU_GP2", "n/a", "n/a", + "GPP_B4", "CPU_GP3", "n/a", "n/a", + "GPP_B5", "ISH_I2C0_SDA", "n/a", "n/a", + "GPP_B6", "ISH_I2C0_SCL", "n/a", "n/a", + "GPP_B7", "ISH_I2C1_SDA", "n/a", "n/a", + "GPP_B8", "ISH_I2C1_SCL", "n/a", "n/a", + "GPP_B9", "I2C5_SDA", "ISH_I2C2_SDA", "n/a", + "GPP_B10", "I2C5_SCL", "ISH_I2C2_SDL", "n/a", + "GPP_B11", "PMCALERT#", "n/a", "n/a", + "GPP_B12", "SLP_S0#", "n/a", "n/a", + "GPP_B13", "PLTRST#", "n/a", "n/a", + "GPP_B14", "SPKR", "TIME_SYNC1", "GSPI0_CS1#", + "GPP_B15", "GSPI0_CS0#", "n/a", "n/a", + "GPP_B16", "GSPI0_CLK", "n/a", "n/a", + "GPP_B17", "GSPI0_MISO", "n/a", "n/a", + "GPP_B18", "GSPI0_MOSI", "n/a", "n/a", + "GPP_B19", "GSPI1_CS0#", "n/a", "n/a", + "GPP_B20", "GSPI1_CLK", "n/a", "n/a", + "GPP_B21", "GSPI1_MISO", "n/a", "n/a", + "GPP_B22", "GSPI1_MOSI", "n/a", "n/a", + "GPP_B23", "SML1ALERT#", "PCHHOT#", "GSPI1_CS1#", + "GSPI0_CLK_LOOPBK", "GSPI0_CLK_LOOPBK", "n/a", "n/a", + "GSPI1_CLK_LOOPBK", "GSPI1_CLK_LOOPBK", "n/a", "n/a", + +}; + +const struct gpio_group tigerlake_pch_lp_group_b = { + .display = "------- GPIO Group GPP_B -------", + .pad_count = ARRAY_SIZE(tigerlake_pch_lp_group_b_names) / 4, + .func_count = 4, + .pad_names = tigerlake_pch_lp_group_b_names, +}; + +const char *const tigerlake_pch_lp_group_c_names[] = { + "GPP_C0", "SMBCLK", "n/a", + "GPP_C1", "SMBDATA", "n/a", + "GPP_C2", "SMBALERT#", "n/a", + "GPP_C3", "SML0CLK", "n/a", + "GPP_C4", "SML0DATA", "n/a", + "GPP_C5", "SML0ALERT#", "n/a", + "GPP_C6", "SML1CLK", "n/a", + "GPP_C7", "SML1DATA", "n/a", + "GPP_C8", "UART0_RXD", "n/a", + "GPP_C9", "UART0_TXD", "n/a", + "GPP_C10", "UART0_RTS#", "n/a", + "GPP_C11", "UART0_CTS#", "n/a", + "GPP_C12", "UART1_RXD", "ISH_UART1_RXD", + "GPP_C13", "UART1_TXD", "ISH_UART1_TXD", + "GPP_C14", "UART1_RTS#", "ISH_UART1_RTS#", + "GPP_C15", "UART1_CTS#", "ISH_UART1_CTS#", + "GPP_C16", "I2C0_SDA", "n/a", + "GPP_C17", "I2C0_SCL", "n/a", + "GPP_C18", "I2C1_SDA", "n/a", + "GPP_C19", "I2C1_SCL", "n/a", + "GPP_C20", "UART2_RXD", "n/a", + "GPP_C21", "UART2_TXD", "n/a", + "GPP_C22", "UART2_RTS#", "n/a", + "GPP_C23", "UART2_CTS#", "n/a", +}; + +const struct gpio_group tigerlake_pch_lp_group_c = { + .display = "------- GPIO Group GPP_C -------", + .pad_count = ARRAY_SIZE(tigerlake_pch_lp_group_c_names) / 3, + .func_count = 3, + .pad_names = tigerlake_pch_lp_group_c_names, +}; + +const char *const tigerlake_pch_lp_group_d_names[] = { + "GPP_D0", "ISH_GP0", "BK0", "n/a", "n/a", "SBK0", "n/a", "n/a", + "GPP_D1", "ISH_GP1", "BK1", "n/a", "n/a", "SBK1", "n/a", "n/a", + "GPP_D2", "ISH_GP2", "BK2", "n/a", "n/a", "SBK2", "n/a", "n/a", + "GPP_D3", "ISH_GP3", "BK3", "n/a", "n/a", "SBK3", "n/a", "n/a", + "GPP_D4", "IMGCLKOUT0", "BK4", "n/a", "n/a", "SBK4", "n/a", "n/a", + "GPP_D5", "SRCCLKREQ0#", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_D6", "SRCCLKREQ1#", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_D7", "SRCCLKREQ2#", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_D8", "SRCCLKREQ3#", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_D9", "ISH_SPI_CS#", "DDP3_CTRLCLK", "n/a", "TBT_LSX2_TXD", "BSSB_LS2_RX", "n/a", "GSPI2_CS0#", + "GPP_D10", "ISH_SPI_CLK", "DDP3_CTRLDATA", "n/a", "TBT_LSX2_RXD", "BSSB_LS2_TX", "n/a", "GSPI2_CLK", + "GPP_D11", "ISH_SPI_MISO", "DDP4_CTRLCLK", "n/a", "TBT_LSX3_TXD", "BSSB_LS3_RX", "n/a", "GSPI2_MISO", + "GPP_D12", "ISH_SPI_MOSI", "DDP4_CTRLDATA", "n/a", "TBT_LSX3_RXD", "BSSB_LS3_TX", "n/a", "GSPI2_MOSI", + "GPP_D13", "ISH_UART0_RXD", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_D14", "ISH_UART0_TXD", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_D15", "ISH_UART0_RTS#", "GSPI2_CS1#", "IMGCLKOUT5", "n/a", "n/a", "n/a", "n/a", + "GPP_D16", "ISH_UART0_CTS#", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_D17", "ISH_GP4", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_D18", "ISH_GP5", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", + "GPP_D19", "I2S_MCLK1", "n/a", "n/a", "n/a", "n/a", "n/a", "n/a", +}; + +const struct gpio_group tigerlake_pch_lp_group_d = { + .display = "------- GPIO Group GPP_D -------", + .pad_count = ARRAY_SIZE(tigerlake_pch_lp_group_d_names) / 8, + .func_count = 8, + .pad_names = tigerlake_pch_lp_group_d_names, +}; + +const char *const tigerlake_pch_lp_group_e_names[] = { + "GPP_E0", "SATAXPCIE0", "SATAGP0", "n/a", "n/a", "n/a", + "GPP_E1", "n/a", "THC0_SPI1_IO2", "n/a", "n/a", "n/a", + "GPP_E2", "n/a", "THC0_SPI1_IO3", "n/a", "n/a", "n/a", + "GPP_E3", "CPU_GP0", "n/a", "n/a", "n/a", "n/a", + "GPP_E4", "SATA_DEVSLP0", "n/a", "n/a", "n/a", "n/a", + "GPP_E5", "SATA_DEVSLP1", "n/a", "n/a", "n/a", "n/a", + "GPP_E6", "n/a", "THC0_SPI1_RST#", "n/a", "n/a", "n/a", + "GPP_E7", "CPU_GP1", "n/a", "n/a", "n/a", "n/a", + "GPP_E8", "n/a", "SATA_LED#", "n/a", "n/a", "n/a", + "GPP_E9", "USB2_OC0#", "n/a", "n/a", "n/a", "n/a", + "GPP_E10", "n/a", "THC0_SPI1_CS#", "n/a", "n/a", "n/a", + "GPP_E11", "n/a", "THC0_SPI1_CLK", "n/a", "n/a", "n/a", + "GPP_E12", "n/a", "THC0_SPI1_IO1", "n/a", "n/a", "n/a", + "GPP_E13", "n/a", "THC0_SPI1_IO0", "n/a", "n/a", "n/a", + "GPP_E14", "DDSP_HPDA", "DISP_MISCA", "n/a", "n/a", "n/a", + "GPP_E15", "ISH_GP6", "Reserved", "n/a", "n/a", "n/a", + "GPP_E16", "ISH_GP7", "Reserved", "n/a", "n/a", "n/a", + "GPP_E17", "n/a", "THC0_SPI1_INT#", "n/a", "n/a", "n/a", + "GPP_E18", "DDP1_CTRLCLK", "n/a", "n/a", "TBT_LSX0_TXD", "BSSB_LS0_RX", + "GPP_E19", "DPP1_CTRLDATA", "n/a", "n/a", "TBT_LSX0_RXD", "BSSB_LS0_TX", + "GPP_E20", "DPP2_CTRLCLK", "n/a", "n/a", "TBT_LSX1_TXD", "BSSB_LS1_RX", + "GPP_E21", "DPP2_CTRLDATA", "n/a", "n/a", "TBT_LSX1_RXD", "BSSB_LS1_TX", + "GPP_E22", "DPAA_CTRLCLK", "DNX_FORCE_RELOAD", "n/a", "n/a", "n/a", + "GPP_E23", "DPPA_CTRLDATA", "n/a", "n/a", "n/a", "n/a", +}; + +const struct gpio_group tigerlake_pch_lp_group_e = { + .display = "------- GPIO Group GPP_E -------", + .pad_count = ARRAY_SIZE(tigerlake_pch_lp_group_e_names) / 6, + .func_count = 6, + .pad_names = tigerlake_pch_lp_group_e_names, +}; + +const char *const tigerlake_pch_lp_group_f_names[] = { + "GPP_F0", "CNV_BRI_DT", "UART0_RTS#", "n/a", + "GPP_F1", "CNV_BRI_RSP", "UART0_RXD", "n/a", + "GPP_F2", "CNV_RGI_DT", "UART0_TXD", "n/a", + "GPP_F3", "CNV_RGI_RSP", "UART0_CTS#", "n/a", + "GPP_F4", "CNV_RF_RESET#", "n/a", "n/a", + "GPP_F5", "n/a", "MODEM_CLKREQ", "CRF_XTAL_CLKREQ", + "GPP_F6", "CNV_PA_BLANKING", "n/a", "n/a", + "GPP_F7", "n/a", "n/a", "n/a", + "GPP_F8", "I2S_MCLK2_INOUT", "n/a", "n/a", + "GPP_F9", "Reserved", "n/a", "n/a", + "GPP_F10", "n/a", "n/a", "n/a", + "GPP_F11", "n/a", "n/a", "THC1_SPI2_CLK", + "GPP_F12", "GSXDOUT", "n/a", "THC1_SPI2_IO0", + "GPP_F13", "GSXSLOAD", "n/a", "THC1_SPI2_IO1", + "GPP_F14", "GSXDIN", "n/a", "THC1_SPI2_IO2", + "GPP_F15", "GSXSRESET#", "n/a", "THC1_SPI2_IO3", + "GPP_F16", "GSXCLK", "n/a", "THC1_SPI2_CS#", + "GPP_F17", "n/a", "n/a", "THC1_SPI2_RST#", + "GPP_F18", "n/a", "n/a", "THC1_SPI2_INT#", + "GPP_F19", "SRCCLKREQ6#", "n/a", "n/a", + "GPP_F20", "EXT_PWR_GATE#", "n/a", "n/a", + "GPP_F21", "EXT_PWR_GATE2#", "n/a", "n/a", + "GPP_F22", "VNN_CTRL", "n/a", "n/a", + "GPP_F23", "V1P05_CTRL", "n/a", "n/a", +}; + +const struct gpio_group tigerlake_pch_lp_group_f = { + .display = "------- GPIO Group GPP_F -------", + .pad_count = ARRAY_SIZE(tigerlake_pch_lp_group_f_names) / 4, + .func_count = 4, + .pad_names = tigerlake_pch_lp_group_f_names, +}; + +const char *const tigerlake_pch_lp_group_h_names[] = { + "GPP_H0", "n/a", "n/a", "n/a", + "GPP_H1", "n/a", "n/a", "n/a", + "GPP_H2", "n/a", "n/a", "n/a", + "GPP_H3", "SX_EXIT_HOLDOFF", "n/a", "n/a", + "GPP_H4", "I2C2_SDA", "n/a", "n/a", + "GPP_H5", "I2C2_SCL", "n/a", "n/a", + "GPP_H6", "I2C3_SDA", "n/a", "n/a", + "GPP_H7", "I2C3_SCL", "n/a", "n/a", + "GPP_H8", "I2C4_SDA", "CNV_MFUART2_RXD", "n/a", + "GPP_H9", "I2C4_SCL", "CNV_MFUART2_TXD", "n/a", + "GPP_H10", "SRCCLKREQ4#", "n/a", "n/a", + "GPP_H11", "SRCCLKREQ5#", "n/a", "n/a", + "GPP_H12", "M2_SKT2_CFG0", "n/a", "n/a", + "GPP_H13", "M2_SKT2_CFG1", "n/a", "n/a", + "GPP_H14", "M2_SKT2_CFG2", "n/a", "n/a", + "GPP_H15", "M2_SKT2_CFG3", "n/a", "n/a", + "GPP_H16", "DDPB_CTRLCLK", "n/a", "PCIE_LNK_DOWN", + "GPP_H17", "DDPB_CTRLDATA", "n/a", "n/a", + "GPP_H18", "CPU_C10_GATE#", "n/a", "n/a", + "GPP_H19", "TIME_SYNC0", "n/a", "n/a", + "GPP_H20", "IMGCLKOUT1", "n/a", "n/a", + "GPP_H21", "IMGCLKOUT2", "n/a", "n/a", + "GPP_H22", "IMGCLKOUT3", "n/a", "n/a", + "GPP_H23", "IMGCLKOUT4", "n/a", "n/a", +}; + +const struct gpio_group tigerlake_pch_lp_group_h = { + .display = "------- GPIO Group GPP_H -------", + .pad_count = ARRAY_SIZE(tigerlake_pch_lp_group_h_names) / 4, + .func_count = 4, + .pad_names = tigerlake_pch_lp_group_h_names, +}; + +const char *const tigerlake_pch_lp_group_r_names[] = { + "GPP_R0", "HDA_BCLK", "I2S0_SCLK", + "GPP_R1", "HDA_SYNC", "I2S0_SFRM", + "GPP_R2", "HDA_SDO", "I2S0_TXD", + "GPP_R3", "HDA_SDI0", "I2S0_RXD", + "GPP_R4", "HDA_RST#", "n/a", + "GPP_R5", "HDA_SDI1", "I2S1_RXD", + "GPP_R6", "n/a", "I2S1_TXD", + "GPP_R7", "n/a", "I2S1_SFRM", +}; + +const struct gpio_group tigerlake_pch_lp_group_r = { + .display = "------- GPIO Group GPP_R -------", + .pad_count = ARRAY_SIZE(tigerlake_pch_lp_group_r_names) / 3, + .func_count = 3, + .pad_names = tigerlake_pch_lp_group_r_names, +}; + +const char *const tigerlake_pch_lp_group_s_names[] = { + "GPP_S0", "SNDW0_CLK", "N/A", + "GPP_S1", "SNDW0_DATA", "N/A", + "GPP_S2", "SNDW1_CLK", "DMIC_CLK_B0", + "GPP_S3", "SNDW1_DATA", "DMIC_CLK_B1", + "GPP_S4", "SNDW2_CLK#", "DMIC_CLK_A1", + "GPP_S5", "SNDW2_DATA", "DMIC_DATA1", + "GPP_S6", "SNDW3_CLK", "DMIC_CLK_A0", + "GPP_S7", "SNDW3_DATA", "DMIC_DATA0", +}; + +const struct gpio_group tigerlake_pch_lp_group_s = { + .display = "------- GPIO Group GPP_S -------", + .pad_count = ARRAY_SIZE(tigerlake_pch_lp_group_s_names) / 3, + .func_count = 3, + .pad_names = tigerlake_pch_lp_group_s_names, +}; + +const char *const tigerlake_pch_lp_group_gpp_t_names[] = { + "GPP_T2", "n/a", "Reserved", + "GPP_T3", "n/a", "Reserved", + +}; + +const struct gpio_group tigerlake_pch_lp_group_t = { + .display = "------- GPIO Group GPP_T (TGL UP3 only) -------", + .pad_count = ARRAY_SIZE(tigerlake_pch_lp_group_gpp_t_names) / 3, + .func_count = 3, + .pad_names = tigerlake_pch_lp_group_gpp_t_names, +}; + +const char *const tigerlake_pch_lp_group_u_names[] = { + "GPP_U4", + "GPP_U5", +}; + +const struct gpio_group tigerlake_pch_lp_group_u = { + .display = "------- GPIO Group GPP_U (TGL UP3 only) -------", + .pad_count = ARRAY_SIZE(tigerlake_pch_lp_group_u_names), + .func_count = 1, + .pad_names = tigerlake_pch_lp_group_u_names, +}; + +const char *const tigerlake_pch_lp_group_gpd_names[] = { + "GPD0", "BATLOW#", + "GPD1", "ACPRESENT", + "GPD2", "LAN_WAKE#", + "GPD3", "PRWBTN#", + "GPD4", "SLP_S3#", + "GPD5", "SLP_S4#", + "GPD6", "SLP_A#", + "GPD7", "n/a", + "GPD8", "SUSCLK", + "GPD9", "SLP_WLAN#", + "GPD10", "SLP_S5#", + "GPD11", "LANPHYPC", +}; + +const struct gpio_group tigerlake_pch_lp_group_gpd = { + .display = "------- GPIO Group GPD -------", + .pad_count = ARRAY_SIZE(tigerlake_pch_lp_group_gpd_names) / 2, + .func_count = 2, + .pad_names = tigerlake_pch_lp_group_gpd_names, +}; + +const struct gpio_group *const tigerlake_pch_lp_community_0_groups[] = { + &tigerlake_pch_lp_group_a, + &tigerlake_pch_lp_group_b, + &tigerlake_pch_lp_group_t, +}; + +const struct gpio_community tigerlake_pch_lp_community_0 = { + .name = "------- GPIO Community 0 -------", + .pcr_port_id = 0x6e, + .group_count = ARRAY_SIZE(tigerlake_pch_lp_community_0_groups), + .groups = tigerlake_pch_lp_community_0_groups, +}; + +const struct gpio_group *const tigerlake_pch_lp_community_1_groups[] = { + &tigerlake_pch_lp_group_s, + &tigerlake_pch_lp_group_h, + &tigerlake_pch_lp_group_d, + &tigerlake_pch_lp_group_u, +}; +const struct gpio_community tigerlake_pch_lp_community_1 = { + .name = "------- GPIO Community 1 -------", + .pcr_port_id = 0x6d, + .group_count = ARRAY_SIZE(tigerlake_pch_lp_community_1_groups), + .groups = tigerlake_pch_lp_community_1_groups, +}; + +const struct gpio_group *const tigerlake_pch_lp_community_2_groups[] = { + &tigerlake_pch_lp_group_gpd, +}; + +const struct gpio_community tigerlake_pch_lp_community_2 = { + .name = "------- GPIO Community 2 -------", + .pcr_port_id = 0x6c, + .group_count = ARRAY_SIZE(tigerlake_pch_lp_community_2_groups), + .groups = tigerlake_pch_lp_community_2_groups, +}; + +const struct gpio_group *const tigerlake_pch_lp_community_4_groups[] = { + &tigerlake_pch_lp_group_c, + &tigerlake_pch_lp_group_e, + &tigerlake_pch_lp_group_f, +}; + +const struct gpio_community tigerlake_pch_lp_community_4 = { + .name = "------- GPIO Community 4 -------", + .pcr_port_id = 0x6a, + .group_count = ARRAY_SIZE(tigerlake_pch_lp_community_4_groups), + .groups = tigerlake_pch_lp_community_4_groups, +}; + + +const struct gpio_group *const tigerlake_pch_lp_community_5_groups[] = { + &tigerlake_pch_lp_group_r, +}; + +const struct gpio_community tigerlake_pch_lp_community_5 = { + .name = "------- GPIO Community 5 -------", + .pcr_port_id = 0x69, + .group_count = ARRAY_SIZE(tigerlake_pch_lp_community_5_groups), + .groups = tigerlake_pch_lp_community_5_groups, +}; + +const struct gpio_community *const tigerlake_pch_lp_communities[] = { + &tigerlake_pch_lp_community_0, + &tigerlake_pch_lp_community_1, + &tigerlake_pch_lp_community_2, + &tigerlake_pch_lp_community_4, + &tigerlake_pch_lp_community_5, +}; + +#endif diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 7cff80f..e7c2b53 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -144,6 +144,20 @@ "Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D (Hewitt Lake)" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SAPPHIRERAPIDS_SP, "Xeon Scalable Processor 4th generation (Sapphire Rapids SP)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_TGL_ID_U_2, + "11th generation (Tiger Lake UP3 family) Core Processor (Mobile)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_TGL_ID_U_4, + "11th generation (Tiger Lake UP3 family) Core Processor (Mobile)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_TGL_ID_Y_2, + "11th generation (Tiger Lake UP4 family) Core Processor (Mobile)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_TGL_ID_Y_4, + "11th generation (Tiger Lake UP4 family) Core Processor (Mobile)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_TGL_ID_H_4, + "11th generation (Tiger Lake H family) Core Processor (Mobile)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_TGL_ID_H_6, + "11th generation (Tiger Lake H family) Core Processor (Mobile)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_TGL_ID_H_8, + "11th generation (Tiger Lake H family) Core Processor (Mobile)" }, /* Southbridges (LPC controllers) */ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "371AB/EB/MB" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10, "ICH10" }, @@ -264,6 +278,16 @@ "Comet Point-LP U Premium/Cometlake" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_BASE, "Comet Point-LP U Base/Cometlake" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERPOINT_U_SUPER, + "Tiger Point U Engineering Sample" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERPOINT_U_PREM, + "Tiger Point U Premium/Tigerlake" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERPOINT_U_BASE, + "Tiger Point U Base/Tigerlake" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_SUPER, + "Tiger Point Y Engineering Sample" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_PREM, + "Tiger Point Y Premium/Tigerlake" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H110, "H110" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H170, "H170" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z170, "Z170" }, @@ -320,6 +344,17 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H81, "H81"}, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_APL_LPC, "Apollo Lake" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_LPC, "Denverton" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H510, "H510" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H570, "H570" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z590, "Z590" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q570, "Q570" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_B560, "B560" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_W580, "W580" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C256, "C256" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C252, "C252" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM570, "HM570" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QM580, "QM580" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WM590, "WM590" }, /* Intel GPUs */ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_G35_EXPRESS, "Intel(R) G35 Express Chipset Family" }, @@ -453,6 +488,18 @@ "Intel(R) Iris Plus Graphics 655" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IRIS_PLUS_G7, "Intel(R) Iris Plus Graphics G7" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGL_GT2_UY, + "Intel(R) Iris Xe Graphics" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGL_GT2_Y, + "Intel(R) Iris Xe Graphics" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGL_GT1, + "Intel(R) UHD Graphics for 11th Gen Intel(R) Processors" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGL_GT1_2, + "Intel(R) UHD Graphics for 11th Gen Intel(R) Processors" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGL_GT2_ULT_1, + "Intel(R) UHD Graphics for 11th Gen Intel(R) Processors" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGL_GT2_ULT_2, + "Intel(R) UHD Graphics for 11th Gen Intel(R) Processors" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UHD_GRAPHICS, "Intel(R) UHD Graphics" }, }; diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 678aa47..f78782e 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -148,6 +148,11 @@ #define PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM 0x9d84 #define PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_PREM 0x0284 #define PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_BASE 0x0285 +#define PCI_DEVICE_ID_INTEL_TIGERPOINT_U_SUPER 0xa081 +#define PCI_DEVICE_ID_INTEL_TIGERPOINT_U_PREM 0xa082 +#define PCI_DEVICE_ID_INTEL_TIGERPOINT_U_BASE 0xa083 +#define PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_SUPER 0xa086 +#define PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_PREM 0xa087 #define PCI_DEVICE_ID_INTEL_H110 0xa143 #define PCI_DEVICE_ID_INTEL_H170 0xa144 #define PCI_DEVICE_ID_INTEL_Z170 0xa145 @@ -196,6 +201,18 @@ #define PCI_DEVICE_ID_INTEL_HM370 0xa30d #define PCI_DEVICE_ID_INTEL_CM246 0xa30e +#define PCI_DEVICE_ID_INTEL_Q570 0x4384 +#define PCI_DEVICE_ID_INTEL_Z590 0x4385 +#define PCI_DEVICE_ID_INTEL_H570 0x4386 +#define PCI_DEVICE_ID_INTEL_B560 0x4387 +#define PCI_DEVICE_ID_INTEL_H510 0x4388 +#define PCI_DEVICE_ID_INTEL_WM590 0x4389 +#define PCI_DEVICE_ID_INTEL_QM580 0x438a +#define PCI_DEVICE_ID_INTEL_HM570 0x438b +#define PCI_DEVICE_ID_INTEL_C252 0x438c +#define PCI_DEVICE_ID_INTEL_C256 0x438d +#define PCI_DEVICE_ID_INTEL_W580 0x438f + #define PCI_DEVICE_ID_INTEL_82810 0x7120 #define PCI_DEVICE_ID_INTEL_82810_DC 0x7122 #define PCI_DEVICE_ID_INTEL_82810E_DC 0x7124 @@ -300,6 +317,13 @@ #define PCI_DEVICE_ID_INTEL_CORE_CML_U1 0x9b51 /* Cometlake U (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_CML_U2 0x9b61 /* Cometlake U (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_CML_U3 0x9b71 /* Cometlake U (Mobile) */ +#define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_U_2 0x9a04 /* Tigerlake UP3 2 Cores */ +#define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_U_4 0x9a14 /* Tigerlake UP3 4 Cores */ +#define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_Y_2 0x9a02 /* Tigerlake UP4 2 Cores */ +#define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_Y_4 0x9a12 /* Tigerlake UP4 4 Cores */ +#define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_H_4 0x9a16 /* Tigerlake H 4 Cores */ +#define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_H_6 0x9a26 /* Tigerlake H 6 Cores */ +#define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_H_8 0x9a36 /* Tigerlake H 8 Cores */ #define PCI_DEVICE_ID_INTEL_HEWITTLAKE 0x6f00 /* Hewitt Lake */ #define PCI_DEVICE_ID_INTEL_SAPPHIRERAPIDS_SP 0x09a2 /* Sapphire Rapids SP */ @@ -372,6 +396,12 @@ #define PCI_DEVICE_ID_INTEL_IRIS_PLUS_655 0x3EA5 #define PCI_DEVICE_ID_INTEL_IRIS_PLUS_G7 0x8A52 #define PCI_DEVICE_ID_INTEL_UHD_GRAPHICS 0x9b41 +#define PCI_DEVICE_ID_INTEL_TGL_GT2_Y 0x9A40 +#define PCI_DEVICE_ID_INTEL_TGL_GT2_UY 0x9A49 +#define PCI_DEVICE_ID_INTEL_TGL_GT1 0x9A60 +#define PCI_DEVICE_ID_INTEL_TGL_GT1_2 0x9A68 +#define PCI_DEVICE_ID_INTEL_TGL_GT2_ULT_1 0x9A78 +#define PCI_DEVICE_ID_INTEL_TGL_GT2_ULT_2 0x9A70 #if !defined(__DARWIN__) && !defined(__FreeBSD__) typedef struct { uint32_t hi, lo; } msr_t; diff --git a/util/inteltool/pcr.c b/util/inteltool/pcr.c index 307dc15..5af7b5e 100644 --- a/util/inteltool/pcr.c +++ b/util/inteltool/pcr.c @@ -125,6 +125,11 @@ case PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_PREM: case PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_BASE: case PCI_DEVICE_ID_INTEL_ICELAKE_LP_U: + case PCI_DEVICE_ID_INTEL_TIGERPOINT_U_SUPER: + case PCI_DEVICE_ID_INTEL_TIGERPOINT_U_PREM: + case PCI_DEVICE_ID_INTEL_TIGERPOINT_U_BASE: + case PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_SUPER: + case PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_PREM: sbbar_phys = 0xfd000000; use_p2sb = false; break; -- To view, visit https://review.coreboot.org/c/coreboot/+/56171 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6071a999be9e8a372997db0369218f297e579d08 Gerrit-Change-Number: 56171 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: supermicro/x11-lga1151-series: Remove SkipExtGfxScan = 1
by Michael Niewöhner (Code Review) 09 Jul '21

09 Jul '21

Attention is currently required from: Nico Huber, Jan Tatje. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56071 ) Change subject: supermicro/x11-lga1151-series: Remove SkipExtGfxScan = 1 ...................................................................... Patch Set 3: (1 comment) Patchset: PS2: > AIUI, these boards don't have display ports connected to the IGD. If […] Exactly, there is no IGD. I see you point, but you're missing one use case: one has the ability to add a PCIe graphics card to the PEG port (each of these boards have at least 1, some 2), too. Since you can't select both PCIe and PEG in FSP, I would use AUTO, so PEG gets detected -- To view, visit https://review.coreboot.org/c/coreboot/+/56071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41249112c65927b61ca5f791f8eb8c3f3d204fce Gerrit-Change-Number: 56071 Gerrit-PatchSet: 3 Gerrit-Owner: Jan Tatje <jan(a)jnt.io> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jan Tatje <jan(a)jnt.io> Gerrit-Comment-Date: Fri, 09 Jul 2021 14:13:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Jan Tatje <jan(a)jnt.io> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/usb4/retimer: Update code to assign correct port number
by Maulik V Vaghela (Code Review) 09 Jul '21

09 Jul '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, John Zhao, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55945 to look at the new patch set (#13). Change subject: drivers/intel/usb4/retimer: Update code to assign correct port number ...................................................................... drivers/intel/usb4/retimer: Update code to assign correct port number Since TBT controller can have maximum 2 ports per controller, our code will loop over DFP structure twice and determine port number. Retimer driver used to assign port number as below: 1. Check if power GPIO is assigned for particular DFP entry or not 2. If entry is there, assign loop count as port number Since loop count is 2, retimer will never assign port number = 2 even if it's present. In case of more than 1 controller, port number assigned will still be 0 or 1 even though actual port index might be 2 or 3. This will create an issue where even if you do transaction on device on controller 2 (port index 2 or 3), EC will route it on port 0 or 1 due to incorrect port index. Update the driver flow as per below to handle this scenario: 1. Check if power GPIO is assigned for particular DFP entry or not 2. Get USB port number from config since it's stored in usb port information under devicetree 3. Pass the port number to ACPI SSDT and EC code Above changes will ensure that we're assigning correct port number as per calculation and EC will use correct port index. BUG=b:189476816 BRANCH=None TEST=Checked that retimer firmware update works on both ports and update happens on correct port index. Change-Id: Ib11637ae39046e0afdacd33bc34e8a59e6f2bfb1 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/drivers/intel/usb4/retimer/chip.h M src/drivers/intel/usb4/retimer/retimer.c 2 files changed, 24 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/55945/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/55945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib11637ae39046e0afdacd33bc34e8a59e6f2bfb1 Gerrit-Change-Number: 55945 Gerrit-PatchSet: 13 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Abhijeet Rao <abhijeet.rao(a)intel.corp-partner.google.com> Gerrit-CC: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/usb/acpi: Create function to get PLD information
by Maulik V Vaghela (Code Review) 09 Jul '21

09 Jul '21

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Tim Wawrzynczak, John Zhao. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, John Zhao, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56024 to look at the new patch set (#8). Change subject: drivers/usb/acpi: Create function to get PLD information ...................................................................... drivers/usb/acpi: Create function to get PLD information Create a separate function to get PLD information from USB device. This is helpful in retimer driver where we can attach same USB port information to retimer instance and we can avoid duplication of information. BUG=None BRANCH=None TEST=Check if code compiles and function returns correct value Change-Id: Iaaf140ce1965dce3a812aa2701ce0e29b34ab3e7 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/drivers/usb/acpi/chip.h M src/drivers/usb/acpi/usb_acpi.c 2 files changed, 23 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/56024/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/56024 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaaf140ce1965dce3a812aa2701ce0e29b34ab3e7 Gerrit-Change-Number: 56024 Gerrit-PatchSet: 8 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Abhijeet Rao <abhijeet.rao(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/adlrvp: Fix DDR5 Boot issue
by Subrata Banik (Code Review) 09 Jul '21

09 Jul '21

Attention is currently required from: Bora Guvendik, Furquan Shaikh, Selma Bensaid, Maulik V Vaghela, Tim Wawrzynczak, Paul Menzel, Meera Ravindranath, Angel Pons, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50996 ) Change subject: mb/adlrvp: Fix DDR5 Boot issue ...................................................................... Patch Set 21: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50996 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9998bfcd12b81c11fcc9f791da2a27d3c788e48a Gerrit-Change-Number: 50996 Gerrit-PatchSet: 21 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 09 Jul 2021 12:51:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: Fix microcode loading
by Patrick Georgi (Code Review) 09 Jul '21

09 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56153 ) Change subject: soc/intel: Fix microcode loading ...................................................................... soc/intel: Fix microcode loading Commit 1aa60a95bd8363d2 broke microcode loading for chipsets that have a microcode blob with a total_size field set to 0. This appears to be support for older chipsets, where the size was set to 0 and assumed to be 2048 bytes. The fix is to change the result of the subtraction to a signed type, and ensure the following comparison is done without promoting the signed type to an unsigned one. Resolves: https://ticket.coreboot.org/issues/313 Change-Id: I62def8014fd3f3bbf607b4d58ddc4dca4c695622 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56153 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Stefan Ott <coreboot(a)desire.ch> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/cpu/intel/microcode/microcode.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Furquan Shaikh: Looks good to me, approved Stefan Ott: Looks good to me, but someone else must approve diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 45996df..469bd25 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -136,9 +136,9 @@ /* header + ucode data blob size */ u32 size = ucode->data_size + sizeof(struct microcode); - size_t ext_tbl_len = ucode->total_size - size; + ssize_t ext_tbl_len = ucode->total_size - size; - if (ext_tbl_len < sizeof(struct ext_sig_table)) + if (ext_tbl_len < (ssize_t)sizeof(struct ext_sig_table)) return NULL; ext_tbl = (struct ext_sig_table *)((uintptr_t)ucode + size); -- To view, visit https://review.coreboot.org/c/coreboot/+/56153 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62def8014fd3f3bbf607b4d58ddc4dca4c695622 Gerrit-Change-Number: 56153 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: ppc64/byteorder.h: define use of big endian
by Patrick Georgi (Code Review) 09 Jul '21

09 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55037 ) Change subject: ppc64/byteorder.h: define use of big endian ...................................................................... ppc64/byteorder.h: define use of big endian All of the build configuration is set to produce big endian image on PPC64. In addition, the toolchain produced by coreboot-sdk does not include little endian libraries so it is not possible to build LE image even when that configuration is changed. This patch changes byte order definition which is required for proper work of functions that deal with endianness, like read_{le,be}*() or {le,be}*toh(). It also revealed bugs related to the endianness on BE targets that are addressed in the following patches. Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> Change-Id: Id31328a832d11db20822733304b0ae477e858d25 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55037 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/arch/ppc64/include/arch/byteorder.h 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/src/arch/ppc64/include/arch/byteorder.h b/src/arch/ppc64/include/arch/byteorder.h index 2485358..79f15b1 100644 --- a/src/arch/ppc64/include/arch/byteorder.h +++ b/src/arch/ppc64/include/arch/byteorder.h @@ -3,6 +3,6 @@ #ifndef _BYTEORDER_H #define _BYTEORDER_H -#define __LITTLE_ENDIAN 1234 +#define __BIG_ENDIAN 4321 #endif /* _BYTEORDER_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/55037 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id31328a832d11db20822733304b0ae477e858d25 Gerrit-Change-Number: 55037 Gerrit-PatchSet: 2 Gerrit-Owner: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maciej Pijanowski Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit July 2021