coreboot-gerrit July 2021

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Change in coreboot[master]: soc/intel/common/irq: Account for single-function devices
by Furquan Shaikh (Code Review) 09 Jul '21

09 Jul '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56173 ) Change subject: soc/intel/common/irq: Account for single-function devices ...................................................................... Patch Set 1: (2 comments) File src/soc/intel/common/block/irq/irq.c: https://review.coreboot.org/c/coreboot/+/56173/comment/8144d8be_02d0e705 PS1, Line 257: IRQ_NONE Should this be `!= IRQ_NONE` or `== IRQ_PIRQ`? What happens if there are multiple functions but only one of them is routed via PIRQ? https://review.coreboot.org/c/coreboot/+/56173/comment/02314096_a778be72 PS1, Line 266: /* Single-function devices must use PIRQ_A */ If there are multi-function devices, is there any requirement on ensuring that at least one is routed to PIRQ_A? -- To view, visit https://review.coreboot.org/c/coreboot/+/56173 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia3b0347c8a2c14413094adf1f9fca380525fb1c8 Gerrit-Change-Number: 56173 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 09 Jul 2021 16:39:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variants/primus: Update GPIO for PS8811 init
by Tim Wawrzynczak (Code Review) 09 Jul '21

09 Jul '21

Attention is currently required from: Nick Vaccaro, Casper Chang. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56157 ) Change subject: mb/google/brya/variants/primus: Update GPIO for PS8811 init ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56157 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia950da61a50f30f7c4aaef572c5ed162ee76dd0e Gerrit-Change-Number: 56157 Gerrit-PatchSet: 2 Gerrit-Owner: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Comment-Date: Fri, 09 Jul 2021 16:38:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Set max Pkg C-states to Auto
by Tim Wawrzynczak (Code Review) 09 Jul '21

09 Jul '21

Attention is currently required from: V Sowmya, Kedar J. Karanje, Maulik V Vaghela, vagdevi.p(a)intel.com, Subrata Banik, Vinay Kumar, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55706 ) Change subject: soc/intel/alderlake: Set max Pkg C-states to Auto ...................................................................... Patch Set 8: Code-Review+2 (1 comment) Patchset: PS7: > C10 is kind of default assignment of the value into MSR and Auto would first read the CPUID leaf 5 a […] Gotcha, thanks for the explanation! -- To view, visit https://review.coreboot.org/c/coreboot/+/55706 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab92eaadad3f17ed8dddc4f383d6eeaab8c9ea6e Gerrit-Change-Number: 55706 Gerrit-PatchSet: 8 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: vagdevi.p(a)intel.com Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: vagdevi.p(a)intel.com Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 09 Jul 2021 16:37:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/irq: Program IRQ pin in irq_program_non_pch()
by Furquan Shaikh (Code Review) 09 Jul '21

09 Jul '21

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Change in coreboot[master]: soc/intel/alderlake: Add missing devices to pci_devs.h
by Furquan Shaikh (Code Review) 09 Jul '21

09 Jul '21

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Change in coreboot[master]: soc/intel/alderlake: Add (and fix) devices in IRQ table
by Tim Wawrzynczak (Code Review) 09 Jul '21

09 Jul '21

Attention is currently required from: Patrick Rudolph. Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56175 ) Change subject: soc/intel/alderlake: Add (and fix) devices in IRQ table ...................................................................... soc/intel/alderlake: Add (and fix) devices in IRQ table Some devices were missing from the IRQ table, and this lack of IRQ programming for the devices (although unused), was causing S0ix entry to fail. BUG=b:176858827 TEST=suspend_stress_test -c10 passes, EC observes SLP_S0IX# toggle correctly upon entry/exit from S0ix Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Ia7612ee008842ba2b8dcd36deb201f4f26130660 --- M src/soc/intel/alderlake/fsp_params.c 1 file changed, 38 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/56175/1 diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 5b0d631..5175cdc 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -80,9 +80,34 @@ }, }, { + .slot = SA_DEV_SLOT_GNA, + .fns = { + ANY_PIRQ(SA_DEVFN_GNA), + }, + }, + { .slot = SA_DEV_SLOT_TCSS, .fns = { ANY_PIRQ(SA_DEVFN_TCSS_XHCI), + ANY_PIRQ(SA_DEVFN_TCSS_XDCI), + }, + }, + { + .slot = PCH_DEV_SLOT_SIO0, + .fns = { + DIRECT_IRQ(PCH_DEVFN_I2C6), + DIRECT_IRQ(PCH_DEVFN_I2C7), + ANY_PIRQ(PCH_DEVFN_THC0), + ANY_PIRQ(PCH_DEVFN_THC1), + }, + }, + { + .slot = PCH_DEV_SLOT_SIO6, + .fns = { + DIRECT_IRQ(PCH_DEVFN_UART3), + DIRECT_IRQ(PCH_DEVFN_UART4), + DIRECT_IRQ(PCH_DEVFN_UART5), + DIRECT_IRQ(PCH_DEVFN_UART6), }, }, { @@ -90,12 +115,23 @@ .fns = { DIRECT_IRQ(PCH_DEVFN_ISH), DIRECT_IRQ(PCH_DEVFN_GSPI2), + ANY_PIRQ(PCH_DEVFN_UFS), + }, + }, + { + .slot = PCH_DEV_SLOT_SIO2, + .fns = { + DIRECT_IRQ(PCH_DEVFN_GSPI3), + DIRECT_IRQ(PCH_DEVFN_GSPI4), + DIRECT_IRQ(PCH_DEVFN_GSPI5), + DIRECT_IRQ(PCH_DEVFN_GSPI6), }, }, { .slot = PCH_DEV_SLOT_XHCI, .fns = { ANY_PIRQ(PCH_DEVFN_XHCI), + DIRECT_IRQ(PCH_DEVFN_USBOTG), ANY_PIRQ(PCH_DEVFN_CNVI_WIFI), }, }, @@ -160,8 +196,8 @@ .fns = { FIXED_INT_ANY_PIRQ(PCH_DEVFN_UART0, PCI_INT_A), FIXED_INT_ANY_PIRQ(PCH_DEVFN_UART1, PCI_INT_B), - ANY_PIRQ(PCH_DEVFN_GSPI0), - ANY_PIRQ(PCH_DEVFN_GSPI1), + DIRECT_IRQ(PCH_DEVFN_GSPI0), + DIRECT_IRQ(PCH_DEVFN_GSPI1), }, }, { -- To view, visit https://review.coreboot.org/c/coreboot/+/56175 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7612ee008842ba2b8dcd36deb201f4f26130660 Gerrit-Change-Number: 56175 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/irq: Program IRQ pin in irq_program_non_pch()
by Tim Wawrzynczak (Code Review) 09 Jul '21

09 Jul '21

Attention is currently required from: Patrick Rudolph. Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56174 ) Change subject: soc/intel/common/irq: Program IRQ pin in irq_program_non_pch() ...................................................................... soc/intel/common/irq: Program IRQ pin in irq_program_non_pch() Previously, irq_program_non_pch() was only programming the IRQ line, but the pin is required as well. BUG=b:176858827 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I2a2823c183a3495721a912de285cddb4a9444c55 --- M src/soc/intel/common/block/irq/irq.c 1 file changed, 6 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/56174/1 diff --git a/src/soc/intel/common/block/irq/irq.c b/src/soc/intel/common/block/irq/irq.c index babfa76..6f1a9e5 100644 --- a/src/soc/intel/common/block/irq/irq.c +++ b/src/soc/intel/common/block/irq/irq.c @@ -432,10 +432,12 @@ continue; } - if (entry->irq) - pci_s_write_config8(PCI_DEV(0, PCI_SLOT(entry->devfn), - PCI_FUNC(entry->devfn)), - PCI_INTERRUPT_LINE, entry->irq); + if (entry->irq) { + pci_devfn_t dev = PCI_DEV(0, PCI_SLOT(entry->devfn), + PCI_FUNC(entry->devfn)); + pci_s_write_config8(dev, PCI_INTERRUPT_LINE, entry->irq); + pci_s_write_config8(dev, PCI_INTERRUPT_PIN, (uint8_t)entry->pin); + } entry = entry->next; } -- To view, visit https://review.coreboot.org/c/coreboot/+/56174 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a2823c183a3495721a912de285cddb4a9444c55 Gerrit-Change-Number: 56174 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/irq: Account for single-function devices
by Tim Wawrzynczak (Code Review) 09 Jul '21

09 Jul '21

Attention is currently required from: Patrick Rudolph. Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56173 ) Change subject: soc/intel/common/irq: Account for single-function devices ...................................................................... soc/intel/common/irq: Account for single-function devices Single-function devices are supposed to always use PIRQ A, therefore ensure this is taken into account when assigning PIRQs. BUG=b:176858827 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Ia3b0347c8a2c14413094adf1f9fca380525fb1c8 --- M src/soc/intel/common/block/irq/irq.c 1 file changed, 17 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/56173/1 diff --git a/src/soc/intel/common/block/irq/irq.c b/src/soc/intel/common/block/irq/irq.c index f0892a9..babfa76 100644 --- a/src/soc/intel/common/block/irq/irq.c +++ b/src/soc/intel/common/block/irq/irq.c @@ -248,13 +248,27 @@ return true; } -static bool assign_pirqs(struct pin_info pin_info[PCI_INT_MAX]) +static bool assign_pirqs(const struct slot_irq_constraints *constraints, + struct pin_info pin_info[PCI_INT_MAX]) { + unsigned int devices = 0; + + for (size_t i = 0; i < MAX_FNS; i++) { + if (constraints->fns[i].irq_route != IRQ_NONE) + ++devices; + } + for (size_t pin_idx = 0; pin_idx < PCI_INT_MAX; pin_idx++) { + enum pirq pirq; if (pin_info[pin_idx].pin_state != SHARED_IRQ_PIN || pin_info[pin_idx].irq != 0) continue; - enum pirq pirq = find_global_least_used_pirq(); + /* Single-function devices must use PIRQ_A */ + if (devices == 1) + pirq = PIRQ_A; + else + pirq = find_global_least_used_pirq(); + if (pirq == PIRQ_INVALID) return false; @@ -317,7 +331,7 @@ if (!assign_shareable_pins(constraints, pin_info, fn_pin_map)) return false; - if (!assign_pirqs(pin_info)) + if (!assign_pirqs(constraints, pin_info)) return false; add_slot_entries(head, constraints->slot, pin_info, fn_pin_map); -- To view, visit https://review.coreboot.org/c/coreboot/+/56173 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia3b0347c8a2c14413094adf1f9fca380525fb1c8 Gerrit-Change-Number: 56173 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Add missing devices to pci_devs.h
by Tim Wawrzynczak (Code Review) 09 Jul '21

09 Jul '21

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56172 ) Change subject: soc/intel/alderlake: Add missing devices to pci_devs.h ...................................................................... soc/intel/alderlake: Add missing devices to pci_devs.h There were some devices missing from pci_devs.h: 1) GNA 2) I2C6 and I2C7 3) UART3, UART4, UART5, UART6 4) UFS 5) GSPI4, GSPI5, GSPI6 BUG=b:176858827 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I2b9f8cceb4bd0c77fc43ef2e48190dd736a84ad8 --- M src/soc/intel/alderlake/include/soc/pci_devs.h 1 file changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/56172/1 diff --git a/src/soc/intel/alderlake/include/soc/pci_devs.h b/src/soc/intel/alderlake/include/soc/pci_devs.h index 1e8ecc7..1729160 100644 --- a/src/soc/intel/alderlake/include/soc/pci_devs.h +++ b/src/soc/intel/alderlake/include/soc/pci_devs.h @@ -56,6 +56,10 @@ #define SA_DEV_TBT2 PCI_DEV(0, SA_DEV_SLOT_TBT, 2) #define SA_DEV_TBT3 PCI_DEV(0, SA_DEV_SLOT_TBT, 3) +#define SA_DEV_SLOT_GNA 0x08 +#define SA_DEVFN_GNA PCI_DEVFN(SA_DEV_SLOT_GNA, 0) +#define SA_DEV_GNA PCI_DEV(0, SA_DEV_SLOT_GNA, 0) + #define SA_DEV_SLOT_TMT 0x0A #define SA_DEVFN_TMT _SA_DEVFN(TMT) #define SA_DEV_TMT _SA_DEV(TMT) @@ -79,20 +83,42 @@ /* PCH Devices */ #define MIN_PCH_SLOT PCH_DEV_SLOT_SIO0 #define PCH_DEV_SLOT_SIO0 0x10 +#define PCH_DEVFN_I2C6 _PCH_DEVFN(SIO0, 0) +#define PCH_DEVFN_I2C7 _PCH_DEVFN(SIO0, 1) #define PCH_DEVFN_THC0 _PCH_DEVFN(SIO0, 6) #define PCH_DEVFN_THC1 _PCH_DEVFN(SIO0, 7) +#define PCH_DEV_I2C6 _PCH_DEV(SIO0, 0) +#define PCH_DEV_I2C7 _PCH_DEV(SIO0, 1) #define PCH_DEV_THC0 _PCH_DEV(SIO0, 6) #define PCH_DEV_THC1 _PCH_DEV(SIO0, 7) +#define PCH_DEV_SLOT_SIO6 0x11 +#define PCH_DEVFN_UART3 _PCH_DEVFN(SIO6, 0) +#define PCH_DEVFN_UART4 _PCH_DEVFN(SIO6, 1) +#define PCH_DEVFN_UART5 _PCH_DEVFN(SIO6, 2) +#define PCH_DEVFN_UART6 _PCH_DEVFN(SIO6, 3) +#define PCH_DEV_UART3 _PCH_DEV(SIO6, 0) +#define PCH_DEV_UART4 _PCH_DEV(SIO6, 1) +#define PCH_DEV_UART5 _PCH_DEV(SIO6, 2) +#define PCH_DEV_UART6 _PCH_DEV(SIO6, 3) + #define PCH_DEV_SLOT_ISH 0x12 #define PCH_DEVFN_ISH _PCH_DEVFN(ISH, 0) #define PCH_DEVFN_GSPI2 _PCH_DEVFN(ISH, 6) +#define PCH_DEVFN_UFS _PCH_DEVFN(ISH, 7) #define PCH_DEV_ISH _PCH_DEV(ISH, 0) #define PCH_DEV_GSPI2 _PCH_DEV(ISH, 6) +#define PCH_DEV_UFS _PCH_DEV(ISH, 7) #define PCH_DEV_SLOT_SIO2 0x13 #define PCH_DEVFN_GSPI3 _PCH_DEVFN(SIO2, 0) +#define PCH_DEVFN_GSPI4 _PCH_DEVFN(SIO2, 1) +#define PCH_DEVFN_GSPI5 _PCH_DEVFN(SIO2, 2) +#define PCH_DEVFN_GSPI6 _PCH_DEVFN(SIO2, 3) #define PCH_DEV_GSPI3 _PCH_DEV(SIO2, 0) +#define PCH_DEV_GSPI4 _PCH_DEV(SIO2, 1) +#define PCH_DEV_GSPI5 _PCH_DEV(SIO2, 2) +#define PCH_DEV_GSPI6 _PCH_DEV(SIO2, 3) #define PCH_DEV_SLOT_XHCI 0x14 #define PCH_DEVFN_XHCI _PCH_DEVFN(XHCI, 0) -- To view, visit https://review.coreboot.org/c/coreboot/+/56172 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b9f8cceb4bd0c77fc43ef2e48190dd736a84ad8 Gerrit-Change-Number: 56172 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: grunt/treeya: add Realtek ALC5682 codec support
by Kevin Chang (Code Review) 09 Jul '21

09 Jul '21

Attention is currently required from: Daniel Kurtz, Martin Roth, Paul Menzel. Kevin Chang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56100 ) Change subject: grunt/treeya: add Realtek ALC5682 codec support ...................................................................... Patch Set 8: (1 comment) File src/mainboard/google/kahlee/variants/treeya/audio.c: https://review.coreboot.org/c/coreboot/+/56100/comment/04e9649b_945e6261 PS4, Line 29: > Update in patchset 7. Correct patchset, it should be patchset 8. -- To view, visit https://review.coreboot.org/c/coreboot/+/56100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49c673fd944b2c2a79c4283eee941a16596ba7fa Gerrit-Change-Number: 56100 Gerrit-PatchSet: 8 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)chromium.org> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alec Wang <alec.wang(a)lcfc.corp-partner.google.com> Gerrit-CC: Allen Cheng <allen.cheng(a)lcfc.corp-partner.google.com> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Daniel Kurtz <djkurtz(a)chromium.org> Gerrit-Attention: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 09 Jul 2021 16:17:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Daniel Kurtz <djkurtz(a)google.com> Comment-In-Reply-To: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-MessageType: comment

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coreboot-gerrit July 2021