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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56163 )
Change subject: Revert "drivers/intel/fsp2_0: use FSP to allocate APEI BERT memory region"
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56163/comment/75503498_ae262b66
PS1, Line 28: TEST=Behavior of the BERT code doesn't change on Mandolin
> would be good if this gets tested on an Intel system with BERT support as well to make sure that thi […]
Verified on ADL, crashlog flow still works.
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Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56178 )
Change subject: WIP: mb/google/guybrush: Enable booting windows
......................................................................
WIP: mb/google/guybrush: Enable booting windows
We can't have a GPE in the _PRW, and a GpioInt in the _CRS. This is an
invalid state according to Windows. For now comment out the wake
configs.
The correct fix still needs more investigation. I think now that the
upstream linux kernel supports [setting wake
states](https://patches.linaro.org/patch/429434/) we might be able to
remove the _PWR object.
BUG=b:186212501
TEST=Boot guybrush to windows
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: Ib130bb4df912024e5148b53e15c92820bb2210d2
---
M src/mainboard/google/guybrush/variants/baseboard/include/baseboard/ec.h
M src/mainboard/google/guybrush/variants/guybrush/overridetree.cb
2 files changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/56178/1
diff --git a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/ec.h
index d73dc00..ff9f1da 100644
--- a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/ec.h
+++ b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/ec.h
@@ -69,7 +69,7 @@
#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */
/* Enable EC sync interrupt */
-#define EC_ENABLE_SYNC_IRQ_GPIO
+// #define EC_ENABLE_SYNC_IRQ_GPIO
/* EC sync irq */
#define EC_SYNC_IRQ GPIO_84
diff --git a/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb b/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb
index 88c7d42..cbc93b7 100644
--- a/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb
+++ b/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb
@@ -81,7 +81,7 @@
register "hid" = ""ELAN0000""
register "desc" = ""ELAN Touchpad""
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)"
- register "wake" = "GEVENT_22"
+ # register "wake" = "GEVENT_22"
register "probed" = "1"
device i2c 15 on end
end
@@ -160,7 +160,7 @@
register "hid" = "ACPI_DT_NAMESPACE_HID"
register "compat_string" = ""google,cros-ec-uart""
register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_21)"
- register "wake" = "GEVENT_5"
+ # register "wake" = "GEVENT_5"
register "uart" = "ACPI_UART_RAW_DEVICE(3000000, 64)"
device generic 0 on
probe FP FP_PRESENT
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Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56177 )
Change subject: soc/amd/cezanne/acpi: Change GPIO controller interrupt to shared
......................................................................
soc/amd/cezanne/acpi: Change GPIO controller interrupt to shared
The Majolica UEFI ACPI tables have this listed as shared. It's already a
level interrupt, so no reason it shouldn't be shared.
This change makes it so Windows can correctly initialize the GPIO
controller.
BUG=b:186212501
TEST=Boot guybrush to windows and see GPIO controller functional. Also
boot guybrush to windows and verify GPIO controller still works.
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: I48c6d548a2a8d67599f25e37eeafc90764d9e2d2
---
M src/soc/amd/cezanne/acpi/mmio.asl
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/56177/1
diff --git a/src/soc/amd/cezanne/acpi/mmio.asl b/src/soc/amd/cezanne/acpi/mmio.asl
index 7b49b85..6126843 100644
--- a/src/soc/amd/cezanne/acpi/mmio.asl
+++ b/src/soc/amd/cezanne/acpi/mmio.asl
@@ -34,7 +34,7 @@
ResourceConsumer,
Level,
ActiveLow,
- Exclusive, , , IRQR)
+ Shared, , , IRQR)
{ 0 }
Memory32Fixed (ReadWrite, ACPIMMIO_GPIO0_BASE, 0x400)
}
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Change subject: AGESA f15tn: Hook up IDS options to Kconfig
......................................................................
Patch Set 5:
(1 comment)
File src/vendorcode/amd/agesa/Kconfig:
https://review.coreboot.org/c/coreboot/+/53985/comment/b44a4602_97ad89a8
PS3, Line 53: default DRIVERS_UART_8250IO
> Good point
I updated the default value. This option is user-visible anyway.
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Hello Mike Banon, build bot (Jenkins), Michał Żygowski, Mike Banon, Arthur Heymans, Kyösti Mälkki, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/53985
to look at the new patch set (#5).
Change subject: AGESA f15tn: Hook up IDS options to Kconfig
......................................................................
AGESA f15tn: Hook up IDS options to Kconfig
IDS (Integrated Debug Services) options are meant to be enabled when one
wants to debug AGESA. Since they are compile-time options, using Kconfig
is the logical choice. Currently, none of the options builds.
Tested with BUILD_TIMELESS=1 without adding the configuration options
into the binary, and Asus A88XM-E does not change.
Change-Id: I465627c19c9856e58ca94aa0efedbddb6baaf3f6
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/cpu/amd/agesa/family15tn/Kconfig
M src/vendorcode/amd/agesa/Kconfig
M src/vendorcode/amd/agesa/f15tn/OptionsIds.h
3 files changed, 62 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/53985/5
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Change subject: supermicro/x11-lga1151-series: Remove SkipExtGfxScan = 1
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS2:
ooof... I only realized now that I messed up my comment at 4:13 PM.
> Exactly, there is no IGD.
Actually I wanted to say: Exactly, there is no ports connected to IGD.
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Change subject: supermicro/x11-lga1151-series: Remove SkipExtGfxScan = 1
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS2:
> Everything else (wrt. PrimaryDisplay) can be handled without FSP.
I doubt it, since there's too much dependencies between various graphics UPDs and possible configurations (IGD fused, unfused, PEG present or nor, PCIe present or not, all three or just two or one, VGA jumper set or unset and all combinations of these). The "fastest solution" would be just using the UPDs (even though, I don't like to rely on FSP, too).
FSP does this:
```
set IVD=1 (pre-mem)
Switchable graphics init (GPIOs, timing, subsystem ids, and some other stuff)
if SkipExtGfxScan == 0
Check for PCIe VGA
Check for PEG VGA and configure it
if IGD not supported e.g. fused (IGD_VID == 0xFFFF) || InternalGfx == 0
IVD = 1
Disable IGD
if InternalGfx == 1 || (PrimaryDisplay == IGD && InternalGfx != 0) # IGfx can be 2 internally o.O
if PrimaryDisplay == IGD
IVD = 0
else
IVD = 1
```
TL;DR IVD does not only depend on SkipExtGfxScan, but also on InternalGfx, PrimaryDisplay
side note: IGD can be enabled with unfused cpus/socs to use it for graphics computing, even without output ports. That's why we don't disable it.
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Change subject: sb/intel/common: Hide IFD options if !HAVE_IFD_BIN
......................................................................
Patch Set 2:
(1 comment)
File src/southbridge/intel/common/firmware/Kconfig:
https://review.coreboot.org/c/coreboot/+/56107/comment/d852b6df_3da01715
PS2, Line 31: depends on HAVE_IFD_BIN
> Is the `depends on HAVE_IFD_BIN` here and for the other configs below unnecessary now? Can it be dro […]
Probably. I could even include IFD_BIN_PATH in the guard.
Personally, I prefer the approach I went with on patchset 1.
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